參數(shù)資料
型號(hào): ADUC834BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁(yè)數(shù): 29/72頁(yè)
文件大小: 1451K
代理商: ADUC834BS
REV.
P
rC (12 March 2002)
ADuC834
29
PRELIMINARY TECHNICAL DATA
ICON (Current Sources Control Register)
Used to control and configure the various excitation and burnout current source options available on-chip.
SFR Address
D5H
Power-On Default Value
00H
Bit Addressable
No
T able IX . ICON SFR Bit Designations
Bit
Name
Description
7
6
---
BO
Reserved for Future Use.
Burnout Current Enable Bit.
Set
by user to enable both transducer burnout current sources in the primary ADC signal paths.
Cleared
by user to disable both transducer burnout current sources.
Auxiliary ADC Current Correction Bit.
Set
by user to allow scaling of the Auxiliary ADC by an internal current source calibration word.
Primary ADC Current Correction Bit.
Set
by user to allow scaling of the Primary ADC by an internal current source calibration word.
Current Source-2 Pin Select Bit.
Set
by user to enable current source-2 (200 μA) to external pin 3 (P1.2/DAC/IEX C1).
Cleared
by user to enable current source-2 (200 μA) to external pin 4 (P1.3/AIN5/IEX C2).
Current Source-1 Pin Select Bit.
Set
by user to enable current source-1 (200 μA) to external pin 4 (P1.3/AIN5/IEX C2).
Cleared
by user to enable current source-1 (200 μA) to external pin 3 (P1.2/DAC/IEX C1).
Current Source-2 Enable Bit.
Set
by user to turn on excitation current source-2 (200 μA).
Cleared
by user to turn off excitation current source-2 (200 μA).
Current Source-1 Enable Bit.
Set
by user to turn on excitation current source-1 (200 μA).
Cleared
by user to turn off excitation current source-1 (200 μA).
5
ADC1IC
4
ADC0IC
3
I2PIN
1
2
I1PIN
1
1
I2EN
0
I1EN
NOT E
1
Both current sources can be enabled to the same external pin, yielding a 400 μA current source.
SF (Sinc Filter Register)
T he number in this register sets the decimation factor and
thus the output update rate for the Primary and Auxiliary
ADCs. T his SFR cannot be written by user software while either
ADC is active. T he update rate applies to both Primary and
Auxiliary ADCs and is calculated as follows:
f
ADC
=
1
3
×
1
8.SF
×
f
MOD
Where:
f
ADC
=
f
MOD
=
SF
=
ADC Output Update Rate
Modulator Clock Frequency = 32.768 kHz
Decimal Value of SF Register
T he allowable range for SF is 0Dhex to FFhex. Examples of SF
values and corresponding conversion update rate (f
ADC
) and
conversion time (t
ADC
) are shown in T able VIII, the power-on
default value for the SF register is 45 hex, resulting in a de-
fault ADC update rate of just under 20 Hz. Both ADC inputs
are chopped to minimize offset errors, which means that the
settling time for a single conversion or the time to a first con-
version result in continuous conversion mode is 2
×
t
ADC
. As
mentioned earlier, all calibration cycles will be carried out
automatically with a maximum, i.e., FFhex, SF value to
ensure optimum calibration performance. Once a calibration
cycle has completed, the value in the SF register will be that
programmed by user software.
T able VIII. SF SFR Bit Designations
SF(dec)
SF(hex)
f
ADC
(Hz)
105.3
19.79
5.35
t
ADC
(ms)
9.52
50.34
186.77
13
69
255
0D
45
FF
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