
REV.
P
rC (12 March 2002)
ADuC834
–
21
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PRELIMINARY TECHNICAL DATA
ME MORY ORGANIZAT ION
T he ADuC834 contains 4 different memory blocks namely:
- 62kBytes of On-Chip Flash/EE Program Memory
- 4kBytes of On-Chip Flash/EE Data Memory
- 256 Bytes of General Purpose RAM
- 2kBytes of Internal X RAM
(1) Flash/E E Program Memory
T he ADuC834 provides 62kBytes of Flash/EE program
memory to run user code. T he user can choose to run code
from this internal memory or run code from an external pro-
gram memory.
If the user applies power or resets the device while the
EA
pin
is pulled low, the part will execute code from the external pro-
gram space, otherwise the part defaults to code execution
from its internal 62kBytes of Flash/EE program memory. Un-
like the ADuC824, where code execution can overflow from the
internal code space to external code space once the PC be-
comes greater than 1FFFh, the ADuC834 does not support the
rollover from F7FFh in internal code space to F800h in exter-
nal code space. Instead the 2048 bytes between F800h and
FFFFh will appear as NOP instructions to user code.
T his internal code space can be downloaded via the UART
serial port while the device is in-circuit.
56kBytes of the program memory can be repogrammed during
runtime hence the code space can be upgraded in the field
using a user defined protocol or it can be used as a data
memory. T his will be discussed in more detail in the Flash/EE
Memory section of the datasheet.
(2) Flash/E E Data Memory
4kBytes of Flash/EE Data Memory are available to the user
and can be accessed indirectly via a group of control registers
mapped into the Special Function Register (SFR) area. Access
to the Flash/EE Data memory is discussed in detail later as part
of the Flash/EE memory section in this data sheet.
(3) General Purpose RAM
T he general purpose RAM is divided into two seperate memo-
ries, namely the upper and the lower 128 bytes of RAM. T he
lower 128 bytes of RAM can be accessed through direct or
indirect addressing while the upper 128 bytes of RAM can
only be accessed through indirect addressing as it shares the
same address space as the SFR space which can only be ac-
cessed through direct addressing.
T he lower 128 bytes of internal data memory are mapped as
shown in Figure 12. T he lowest 32 bytes are grouped into
four banks of eight registers addressed as R0 through R7. T he
next 16 bytes (128 bits), locations 20Hex through 2FHex
above the register banks, form a block of directly addressable
bit locations at bit addresses 00H through 7FH. T he stack can
be located anywhere in the internal memory address space, and
the stack depth can be expanded up to 2048 bytes.
Reset initializes the stack pointer to location 07 hex and incre-
ments it once before loading the stack to start from locations 08
hex which is also the first register (R0) of register bank 1. T hus,
if one is going to use more than one register bank, the stack
pointer should be initialized to an area of RAM not used for data
storage.
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS
R0 R7
BANKS
SELECTED
VIA
BITS IN PSW
11
10
01
00
07H
0FH
17H
1FH
2FH
7FH
00H
08H
10H
18H
20H
RESET VALUE OF
STACK POINTER
30H
GENERAL-PURPOSE
AREA
Figure 12. Lower 128 Bytes of Internal Data Memory
T he ADuC834 contains 2048 bytes of internal X RAM, 1792
bytes of which can be configured to be used as an extended 11-
bit stack pointer.
By default the stack will operate exactly like an 8052 in that it
will rollover from FFh to 00h in the general purpose RAM. On
the ADuC834 however it is possible (by setting CFG834.7) to
enable the 11-bit extended stack pointer. In this case the stack
will rollover from FFh in RAM to 0100h in X RAM.
T he 11-bit stack pointer is visable in the SP and SPH SFRs.
T he SP SFR is located at 81h as with a standard 8052. T he
SPH SFR is located at B7h. T he 3 LSBs of this SFR contain
the 3 extra bits necessary to extend the 8-bit stack pointer into
an 11-bit stack pointer.
UPPER 1792
BYTES OF
ON-CHIP XRAM
(DATA +STACK
FOR EXSP=1,
DATA ONLY
FOR EXSP=0)
256 BYTES OF
ON-CHIP DATA
RAM
(DATA + STACK)
LOWER 256
BYTES OF
ON-CHIP XRAM
(DATA ONLY)
00H
FFH
100H
00H
07FFH
CFG834.7 = 0
CFG834.7 = 1
Figure 13. Extended Stack Pointer Operation