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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 8/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-8
MD400158/D
Pin
Pin Name
TXD[3:0]_4
I/O
O
Description
Transmit Data Port 4
In standard 10 Mbit/sec Serial Mode, TXD0_4 is the serial transmit data output from
port #4 to the encoder. In MII mode, these outputs drive a nibble of transmit data
every leading edge of the TXC_4 clock from port #4 to the encoder.
198, 199
201, 202
143
TXEN_1
O
Transmit Enable Port 1
This output from port #1 is used to activate the encoder. In standard 10 Mbit/sec
Serial Mode, it becomes active when the first bit of the Preamble is transmitted and
inactive when the last bit of the frame is transmitted. In MII mode, this output
becomes active when the first nibble of the Preamble is transmitted and inactive
when the last nibble of the frame is transmitted. This output is active high.
167
TXEN_2
O
Transmit Enable Port 2
This output from port #2 is used to activate the encoder. In standard 10 Mbit/sec
Serial Mode, it becomes active when the first bit of the Preamble is transmitted and
inactive when the last bit of the frame is transmitted. In MII mode, this output
becomes active when the first nibble of the Preamble is transmitted and inactive
when the last nibble of the frame is transmitted. This output is active high.
186
TXEN_3
O
Transmit Enable Port 3
This output from port #3 is used to activate the encoder. In standard 10 Mbit/sec
Serial Mode, it becomes active when the first bit of the Preamble is transmitted and
inactive when the last bit of the frame is transmitted. In MII mode, this output
becomes active when the first nibble of the Preamble is transmitted and inactive
when the last nibble of the frame is transmitted. This output is active high.
203
TXEN_4
O
Transmit Enable Port 4
This output from port #4 is used to activate the encoder. In standard 10 Mbit/sec
Serial Mode, it becomes active when the first bit of the Preamble is transmitted and
inactive when the last bit of the frame is transmitted. In MII mode, this output becomes
active when the first nibble of the Preamble is transmitted and inactive when the last
128
RXC_1
I
Receive Clock Port 1
In standard 10Mbit/sec Serial Mode, this input is a 10Mhz, 50% duty cycle nominal
receive clock which is used to synchronize incoming data from the decoder to port
#1. In 10Mbit/sec Serial Mode CSN and RXD0_1 are assumed to transition from the
leading edge of this clock. In MII mode this clock is a 2.5/25 Mhz, 50% duty cycle
receive clock that synchronizes incoming nibble wide data from the decoder to port
#1. In MII mode data and the RXDV signal are assumed to transition from the falling
edge of the clock.
146
RXC_2
I
Receive Clock Port 2
In standard 10Mbit/sec Serial Mode, this input is a 10Mhz, 50% duty cycle nominal
receive clock which is used to synchronize incoming data from the decoder to port
#2. In 10Mbit/sec Serial Mode CSN and RXD0_2 are assumed to transition from the
leading edge of this clock. In MII mode this clock is a 2.5/25 Mhz, 50% duty cycle
receive clock that synchronizes incoming nibble wide data from the decoder to port
#2. In MII mode data and the RXDV signal are assumed to transition from the falling
edge of the clock.
Pin Description (cont.)
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