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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 28/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-28
MD400158/D
3.6.5 Receive Command Register
A port’s Receive Command Register has two primary
functions, it specifies the Address Match Mode, and it
specifies which types of receive frames will be received
and if an associated interrupt will be produced. To set
interrupt conditions the Receive Command Register uses
bits 5 through 0 in conjunction with bit #7 of configuration
register #1.
Bit 7 of configuration register #1 is a general receive
interrupt disable. Setting this bit HIGH disables all receive
interrupt conditions even f one of the bits 0 through 5 n the
receive command register is set HIGH. This allows ena-
bling reception of receive packets with errors without an
interrupt being produced. With the general receive inter-
rupt bit LOW, a receive interrupt can be produced on one
or more of he ollowing conditions by setting ts associated
interrupt enable bit in the receive command register:
Receive Command Register Format
7
6
5
4
3
2
1
0
Receive
Command
Register
Receive
Command
Register
Values
Definition
R/W*
Default
Values
Upon Reset
Bit 0
1
Enables Reception of packets with a receive overflow error
without generating an RXDC.
Automatically discards packets with a receive overflow error
generating an RXDC.
Enables Reception of packets with a receive CRC error
without generating an RXDC.
Automatically discards packets with a receive CRC error
generating an RXDC.
Enables Reception of oversized packets without generating
an RXDC.
Automatically discards oversized packets generating
an RXDC.
Enables Reception of undersized packets without generating
an RXDC.
Automatically discards undersized packets generating
an RXDC.
Depending on the value of Bit #7 of Configuration Register
#3, this bit can be used as an indication of the first 12
bytes received.
Depending on the value of Bit #7 of Configuration Register
#3, this bit can be used as an indication of the reception of
a good packet for debugging purposes.
Please Refer to the following table for match mode definitions
R/W
0
0
R/W
0
Bit 1
1
R/W
0
0
R/W
0
Bit 2
1
R/W
0
0
R/W
0
Bit 3
1
R/W
0
0
R/W
0
Bit 4
1
R/W
0
Bit 5
1
R/W
0
Bit 6
Bit 7
Note:
Bit 7 of configuration register #1 is a general receive interrupt disable mode. Setting this bit HIGH will prevent a
interrupt from being generated even if one of the bits 0 through 5 in the receive command register is set HIGH. This enables
the reception of receive packets with errors without generating an interrupt.
*This register can be used as a write only or a Read/Write register by configuring the address input accordingly. Please
refer to “3.6.1 Internal Port Register Addressing Table” for details.
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