參數(shù)資料
型號(hào)： 84301
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 38/62頁(yè)
文件大?。?/td> 606K
代理商： 84301
84301 4-Port
Fast Ethernet Controller
4-38
MD400158/D
will be provided to the 8-Bit Register Interface with Big
Endian Byte Ordering. For most of the counters 4 read
operations are required to completely read the counter
value. The only exception to this is if bit 2 of Configuration
Register #3 is 0, then the counters mentioned in the
description of that bit’s function will require only 2 reads to
completely read hem. The value of he counter being read
will be held upon detection of the first byte read operation.
The counter value will be held until completion of the read
that reads out the least significant byte of the counter.
Once all bytes of a counter have been read, what happens
to the counter value depends upon the value of the bit 3 of
Configuration Register #3 and is described in the section
below.
3.7.2 Counter Value After Read Operation Completion
Depending on the value written to bit 3 of Configuration
Register #2 the value of a counter after the east significant
byte has been read will either be preset to a value or reset
to 00000000 hex dependent upon the following:
1. If bit 3 is set in Configuration Register #3, then after
the last byte of the counter is read, the counter will
be cleared to zero if no attempts were made to
increment the counter while ts value was being held.
If a port tries to update a counter when it’s value was
being held due to a read operation in progress, then
once the least significant byte of the counter has
been read, the counter will be preset to the
count value it would have if the counter had
started from zero and been incremented once.
2. If bit 3 is not set in Configuration Register #3 then
after the last byte of the counter is read the counter
will simply maintain its present value or, be incre
mented after the least significant byte is read if a
port attempted to increment the counter while the
counter value was being held due to a read operation
in progress.
3.7.3 Counter Behavior Upon Reaching Maximum
Count
When a counter reaches ts maximum count (all bits are 1),
the counter will not be allowed to increment further. The
counter will be held at the maximum count until completion
of a read operation to the counter causes its value to
change according to the description given in item 1 of
section 3.7.2, with the exception that n this case the actual
value of bit 3 in Configuration Register #3 is ignored.
Because the counter has overflowed, only those attempts
to ncrement the counter while t was frozen for reading will
be reflected in the new preset value. Any counter events
that occurred while the counter was frozen prior to the
beginning of being read are lost.
3.7.4 Counter Interrupt Conditions
3.7.4.1 Enabling Counter Interrupts
Writing any of the bits of either of the Counter Interrupt
Enable Registers #1 or #2 will enable the assertion of an
interrupt on the interrupt pin INT [4:1] for that port, should
the associated counter reach a condition described in the
next section. To determine if one or more counters have
caused an nterrupt condition, the Counter Interrupt Status
Registers can be read. Once a counter has reached a
condition described in section 3.7.4.2 its associated bit in
the Counter Interrupt Status Register will be set ndepend-
ent of he setting of ts associated Counter nterrupt Enable
Register bit. To clear an interrupt condition either one or
both the counters nterrupt status registers has to be read.
3.7.4.2 Counter Attention Conditions
Each N-bit counter has a unique “Counter Attention Con-
dition” bit which s automatically set when the count for the
N-bit counter reaches a count of 80000000 hex which is
half full of ts terminal count of FFFFFFFF hex. The half full
condition s specified to occur when the most significant bit
of the counter transitions from a 0 to a 1.
These “attention bits” are stored in the Counter Interrupt
Status Register #1 and #2. These registers are 8-bits
wide. Writes to these registers will have no effect. Note
that the contents of the Counter Interrupt Status Registers
will be cleared after it is read.
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