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參數(shù)資料
| 型號(hào)： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 29/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-29
MD400158/D
Match
Mode
1
0
0
1
Match
Mode
0
0
1
0
Function
Receiver Disable
Receive All Frames
Receive Station or Broadcast
Frames
Receive Station,
Broadcast/Multicast Frames
0
1
2
3
1
1
3.6.6 Receive Status Register
Within each port’s receive section there s a receive status
register that is written with the status of each receive
packet whether it is discarded or not. Once the receive
status register s written, bit 7 of he register s set o a 0 and
the register is write protected from being overwritten with
new status until it is read. Reading the receive status
register clears the register and enables t to be written with
new status. The following packet status is reported in the
receive status register:
Receive Status Register Format
7
6
5
4
3
2
1
0
Bit
Value
Definition
R/W
Default
0
‘1’
Indicates that a frame with an
overflow error has been received.
R
0
1
‘1’
Indicates that a frame with a CRC
error has been received.
R
0
2
‘1’
Indicates that a frame with dribble
bits or nibbles has been received.
R
0
3
‘1’
Indicates that a short frame has
been received.
R
0
4
‘1’
Indicates that an oversized frame
has been received.
R
0
5
‘1’
Indicates that a good frame has
been received.
R
0
6
‘1’
Indicates that the first 12 bytes of
a frame has been received.
R
0
7
‘1/0’
Indicates old (1) /new (0) status
R
0
NOTE
Changing the receive Match Mode bits during frame re-
ception may change chip operation and give unpredictable
results.
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