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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-31
MD400158/D
programmed in the station address register that the
packet will not be rejected due to incorrect address
even its last 4 bits did not match.
Mode B: Transmit Packet Autopad Mode
This feature automatically pads packets to be trans-
mitted with ess han 60 bytes of data out o a minimum
IEEE 802.3 standard packet length of 60 bytes ex-
cluding FCS. Padding is done with bytes of 00 hex in
10 Mbit/sec Serial Mode and 55 hex in MII mode.
Mode C: Transmit No Preamble Mode
This mode prevents the transmitter from adding a
preamble pattern at the beginning of data to be
transmitted.
Mode D: Receive Own Transmit Disable Mode
This mode prevents a port from receiving a packet if
it is also transmitting a packet. Please refer to Table
A for details.
Mode E: Transmit No CRC Mode
This mode prevents a port’s transmitter from append-
ing transmit data with an FCS.
Mode F: Full Duplex Mode
In this mode a ports transmitter will ignore carrier
sense and will not defer to it if it is ready to transmit a
packet.
The software bit setting and the hardware setting (pin
#123, 124, 125 or 127) have an OR relationship. This
means hat either he hardware or software setting will
enable Full Duplex.
Note:
Bit 3 setting will vary according to the
Full Duplex or Half Duplex setting. Please refer
to Table A for details.
Mode G: Receive CRC Mode
In this mode a ports receiver oads the 4 bytes of FCS
into the receive FIFO along with the data allowing the
FCS value to be read out.
Mode H: Disable Receive Interrupts
With this bit set a ports receiver is disabled from
producing receive interrupts.
Full Duplex/Half Duplex Modes
Operation with Receive Own Transmit Disable. TABLE A
The following description assumes that a transceiver
is connected to the MAC.
Bit 3
1
Bit 5
0
(Default)
Mode
Half
Duplex
Functional Description
In this mode the transmit data looped back from the
transceiver is ignored by the controller. The data does
not get written into the receive FIFO and the Rxrdy
does not reflect the incoming data.
In this mode the transceiver (In Full Duplex mode) will
not loopback the transmitted data. However, since data
reception is possible during transmission, bit 3 should be
written with ‘0’ so that the data gets written to the
Receive FIFO.
In normal Half Duplex operation the PHY loops back the
transmitted data back to the MAC. In other words, the PHY
always loops back the transmitted data in half duplex
mode. As far as the controller is concerned, it knows that
the data coming back is it’s own transmitted packet and
since bit 3 is not set, the transmitted packet gets written
into the receive FIFO.
Reserved
0
(Default)
1
Full
Duplex
0
(Default)
0
(Default)
Loopback
Mode
1
1
Note:
There is no internal loopback within the MAC. Loopback is dependent on a PHY
connected to the MAC.
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