參數(shù)資料
型號: 84301
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(4端口快速以太網(wǎng)控制器)
文件頁數(shù): 2/62頁
文件大小: 606K
代理商: 84301
84301 4-Port
Fast Ethernet Controller
4-2
MD400158/D
Table of Contents
1.0 Pin Description
2.0 Introduction
3.0 Functional Description
3.1 Frame Format
3.2 Packet Transmission per Port
3.2.1 Controlling Transmit Packet
Encapsulation
3.2.2 Transmission Initiation/Deferral
3.2.3 Collision on Transmit
3.2.4 Transmit Termination Conditions
3.2.5 Conditions That Will Cause a Port’s
TXRET Pin to go HIGH
3.2.6 Detecting and Clearing a
Transmit Retry Condition
3.3. Packet Reception Per Port
3.3.1 Preamble Processing
3.3.2 Address Matching
3.3.3 Terminating Reception
3.3.4 Using the RXABORT Pins to Terminate
Reception of a Packet
3.3.5 Receive Discard Conditions
3.4 System Interface
3.5 FIFO Interface
3.5.1 Little Endian and Big Endian Format
3.5.2 Transmit FIFO Interface
3.5.3 Receive FIFO Interface
3.5.4 Special Conditions on
RXRD_TXWR Clock Input
3.6 Register Interface
3.6.1 Internal Port Register Addressing
Table
3.6.2 Station Address Register
3.6.3 Transmit Command Register
3.6.4 Transmit Status Register
3.6.5 Receive Command Register
3.6.6 Receive Status Register
3.6.7 Configuration Registers
3.6.8 FIFO Threshold Register
3.6.9 Defer Register Calculations for
the 84301
3.6.10 Transmit Control/Product I.D. Register
3.6.11 Full Duplex Status Register
3.7 Counters
3.7.1 Accessing the Counters
3.7.2 Counter Value after Read Operation
Completion
3.7.3 Counter Behavior Upon Reading
Maximum Count
3.7.4 Counter Interrupt Condition
4.0 DC Characteristics
5.0 Command/Status Interface Timing
5.01 Command/Status Interface Read Timing
5.02 Command/Status Interface Write Timing
6.0 Transmit Interface Timing
6.01 Ethernet Transmit Interface Timing
6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Write Timing
7.01 Transmit Data Interface Write Timing 1
7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Read Timing
8.01 Receive Data Interface Read Timing 1
8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on
Exception Conditions
10.0 Receive Data Interface Timing on
Exception Conditions
11.0 Reset Timing
Illustrations
Figure 1. Functional Block Diagram of the 84301
Figure 2. 84301 Pin Configuration
Figure 3. Typical Application Example
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