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參數資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網控制器) |
| 中文描述： | 4端口快速以太網控制器（4端口快速以太網控制器） |
| 文件頁數： | 17/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-17
MD400158/D
interval begun. The counter that keeps track of the
number of collisions is modulo 16 and therefore rolls
over on the 17th collision. Bits 15 to 11 of a port’s
transmit collision counter allow a user to determine
how many transmission attempts were necessary to
successfully transmit the packet.
Late Collision:
If a Collision occurs greater than 64
byte imes after he ransmission begins his s consid-
ered a late collision error. Upon this condition the
transmission is terminated, the TXRET output is
driven HIGH, and the late collision status bit is set.
At the completion of every transmission or retransmission,
new status information is loaded into the Transmit Status
Register. Dependent upon the bits enabled in the Trans-
mit Command Register, an interrupt will be generated for
the just completed transmission.
3.2.5 Conditions That Will Cause a Port’s TXRET Pin
to go High
Detection of a HIGH value on one of the chips 4 TXRET
pins indicates that the associated port could not complete
transmission of a packet due to one or more of the
following conditions:
1. A transmit FIFO underflow occurred while
transmitting the packet.
2. A late collision occurred while transmitting
the packet.
3. Carrier sense never went active during
transmission or went from an active to inactive
state during transmission.
4. 16 attempts to transmit the packet all resulted in
transmit collisions.
5. The ONETRYMODE pin is HIGH and a
collision occurs.
Any of the above conditions will cause the port to flush the
transmit FIFO and initiate a transmit retry request. With
initiation of a transmit Retry Request the port’s TXRDY
output will go low and stay low until the TXRET flag is
cleared. Similar to a port's receive discard signal, a
transmit retry signal going to the external TXRET pin is
latched upon a transmit retry condition and held high until
Figure 3. Typical Application Example
TRANSMIT
RECEIVE
DATA
BUFFER
BUS
TRANSCEIVER
DMA/
BUFFER
CONTROL
CPU
SYSTEM
MEMORY
84301
4 CHANNEL
QUAD
RJ 45
RJ 45
RJ 45
RJ 45
FILTERS
80C240 10/100Base-T4
or 80220/21 10/100Base-TX
MEDIA INTERFACE
ADAPTER WITH ONCHIP
80C240 10/100Base-T4
or 80220/21 10/100Base-TX
MEDIA INTERFACE
ADAPTER WITH ONCHIP
FILTERS
80C240 10/100Base-T4
or 80220/21 10/100Base-TX
MEDIA INTERFACE
ADAPTER WITH ONCHIP
FILTERS
80C240 10/100Base-T4
or 80220/21 10/100Base-TX
MEDIA INTERFACE
ADAPTER WITH ONCHIP
FILTERS
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