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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 6/62頁 |
| 文件大小： | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-6
MD400158/D
Pin Description (cont.)
Pin
Pin Name
I/O
Description
Transmit and Receive Exception Indicators
48, 62
TXRET_[1:4]
71, 79
O
Transmit Retry
These are active high tristate outputs. All four of these output pins are driven by
tristate drivers enabled by an active low being driven onto the TXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port
could not complete transmission of a packet due to one of the following conditions
and that a retransmission of the packet is requested:
1. A late collision occurred during transmission.
2. Carrier sense never went high or dropped out
during transmission.
3. During a transmission attempt a transmit FIFO underflow error occurred.
4. 16 attempts to transmit the packet all resulting in transmit collisions.
Internally, the TXRET signal will remain high until it is cleared by the CLRTXERR pin,
(See the text on clearing error conditions). As long as the internal TXRET signal for
a port remains high, that port’s transmit FIFO will remain cleared and no new
transmissions can occur.
Receive Discard
These are active high tristate outputs. All four of these outputs pins are driven
by tristate drivers enabled by a low value being driven onto the RXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port
discarded reception of a packet due to one of the possible receive discard conditions.
Internally, a port’s RXDC signal will remain high until it is cleared by the CLRRXERR
pin, (See the text on "Receive Discard Conditions"). As long as the internal RXDC
signal for a port remains high, that port’s receive FIFO will remain cleared and no new
packets will be received.
45, 58
65, 74
RXDC_[1:4]
O
Special Purpose Pins
38
CLRTXERR
I
Clear Transmit Error
This active high input is used to clear transmit retry flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
Clear Receive Error
This active high input is used to clear Receive Discard flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
Receive Abort
These inputs, when pulse high concedes the corresponding port to abort
reception of a frame.
50
CLRRXERR
I
46, 59
67, 75
RXABORT_[1:4]
I
127, 125
124, 123
FDUPLX_[1:4]
I
Full Duplex Mode
These active low inputs are used to set the corresponding port into Full Duplex mode.
In this mode, the corresponding transmitter will not defer to an active carrier
sense signal.
152
ONETRYMODE
I
This input when tied high will cause any of the 84301 ports to drive it’s correspond-
ing TXRET to a HIGH state for a particular port if during transmission it encounters
a collision contention. The controller will not automatically attempt to retransmit a
packet/frame when this input pin is high. Transmit FIFO is flushed of data and the
new packet/frame needs to be reloaded to the FIFO for transmission.
ONETRYMODE has an internal pull-down.
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