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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 35/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-35
MD400158/D
Bits 4 thru 7 - Unused. These bits when read will have a
0 value.
3.6.8 FIFO Threshold Register
This register allows programming of the threshold of
Space Available and/or Data Available double word
counts that cause assertion of the TxRDY and/or RxRDY
signals respectively. Bits 4 through 7, when written with a
binary value, indicates the minimum number of double
words necessary in the receive FIFO before RxRDY is
asserted. Similarly, bits 0 through 3, when written with a
binary value, ndicate he minimum number of double word
wide spaces necessary in the transmit FIFO for TxRDY to
be asserted. Table 3.6.8.1 shows how many double
words of space/data are required to cause the TXRDY/
RXRDY signals to go high for each threshold setting.
3.6.9 Defer Register Calculations for the 84301
Defer Time Definitions
In the standard Half Duplex Mode, Defer time s defined as
the time from the falling edge of carrier sense to the rising
edge of TXEN. In full duplex mode, the defer time is
measured as the time from the falling edge of TXEN to the
next rising edge of TXEN. The binary value programmed
into he defer count register s used o determine how many
byte times the defer time will be set to. The algorithms
below illustrates how the defer time is calculated.
The defer time is split into two periods. The first period is
the first 2/3 and the second period is the second 1/3 of the
defer time. The defer time calculated by the following
algorithms are for the first 2/3 of the defer period only. For
further details, please refer to the section 3.2.2.
Algorithm for Defer Time Calculations for MII
Defer Time = Int{{ nt (Delay /40) + 5 + DefRegSet}/2} + 2
Defer Time = The transmit defer time in byte times
Delay
= Delay rom he alling edge of TXEN o he alling
edge of CSN. (Half Duplex)
= 0 (Full Duplex)
DefRegSet = The transmit defer register setting
Int = Using the Whole Number Portion
Example Calculations
To find out the value that needs to be programmed nto the
defer register for a defer time of 960 ns, the following steps
need to be taken
Assume Delay = 340 ns
Desired Defer Time = 960 ns = 12 byte times
Note: The desired defer time should be a multiple
of 80
Fifo Threshold Register Bits
Minimum # of
Double Words of
Data for RXRDY High
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Minimum # of
Double Word Spaces
for TXRDY High
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3.6.8.1 FIFO Threshold Register Settings Table
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