參數(shù)資料
型號(hào)： 84301
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 61/62頁(yè)
文件大小： 606K
代理商： 84301
84301 4-Port
Fast Ethernet Controller
4-61
MD400158/D
Page 57: 208 Pin PQFP Dimension Diagram
- Reference to 4.25 Max. has changed to 4.10 Max.
- Reference to 3.75
±
0.10 has changed to 3.40
±
0.20.
- Reference to 0.25 - 0.40 has changed to 0.25 Min.
4/9/97:
- Latest version MD400158/C
- All references to RXRD_TXWR, have been changed to RXRD_TXWR.
Page 3: - Pin 4, Description, reference to A[2:0] has been changed to A[4:0], reference to REGPS[1:0] has been
changed to REGPS[1:0].
- Pin 5, Description, reference to A[2:0] has been changed to A[4:0], reference to REGPS[1:0] has been
changed to REGPS[1:0].
- Pin 21,20, Pin Name, REGPS[1:0] has been changed to REGPS[1:0].
- Pin 21,20, Description, REGPS1 has been changed to REGPS1, also REGPS1, REGPS0 , Selected
Port, Table has been added.
- Pin 49, Description, This input is an... copy has been changed to... This input is an active low asynchronous chip
reset. After reset, all registers except the Hash and Station Address registers are reset to zero, all FIFOs are
cleared, all counters are reset to zero.
Page 4: - Pin 30,29, Description, Table RXTXPS[1:0] has been added.
Page 12: - Pagination change has occurred.
Page 15: - End of Section 3.2.1 Controlling Transmit Packet Encapsulation, Table Transmit No CRC has been added,
also paragraph Please note that both ... has been added.
Page 19: - Section 3.3.4 Using the RXABORT Pins to Terminate Reception of a Packet, paragraph one, By pulsing
the corresponding... copy has changed to ...By pulsing the corresponding RXABORT pin high for a
minimum of 1 RXC cycle any time during the reception of a packet, that particular port’s packet reception
can be terminated.
Page 24: - 3.6.1 Internal Port Register Addressing Table, Reference to Short Frame Counter, has been changed to
Runt Frame Counter.
Page 35: - Section 3.6.9 Defer Register Calculations for the 84301, last paragraph The defer time is split... has
been added.
Page 45: - 5.01 Command/Status Interface Read Timing, Reference to A0-A3 has been changed to A0-A4.
- 5.02 Command/Status Interface Write Timing, Reference to A0-A3 has been changed to A0-A4.
Page 47: - 7.0 Transmit Data Interface Write Timing
- t
8
(min) 0 ns has been changed to 0.5 ns.
Page 48: - 7.01 Transmit Data Interface Write Timing 1
- Timing TXNOCRC, has been changed.
Page 49: - 7.01 Transmit Data Interface Write Timing 2
- Timing TXNOCRC, has been changed.
3/20/98:
- Latest version MD400158/D
Page 2 - Table of Contents Reference to 11.0 Reset Timing added.
Page 57 - 11.0 Reset Timing Table and Timing Diagram added.
Revision History
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