參數(shù)資料
型號: 84301
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(4端口快速以太網(wǎng)控制器)
文件頁數(shù): 36/62頁
文件大小: 606K
代理商: 84301
84301 4-Port
Fast Ethernet Controller
4-36
MD400158/D
Step 1: Calculation of the Actual Defer Time
Let’s assume a Defer Register Setting Value of 10
Defer Time = Int{ {Int (Delay / 40) + 5 + DefRegSet}
/2} + 2
= Int { { Int ( 8.5 ) + 5 + 10 }/2} + 2
= Int { 11.5 } + 2
= 11 + 2 = 13 byte times
Step 2: Calculation of the Actual Defer
Register Setting
Since we know that the value derived from the
previous step is 1 byte time greater than what
is desired we will decrement the assumed
defer register setting by 3 and do the
calculations again.
Let’s assume a Defer Register Setting Value of 7
Defer Time = Int { {Int(Delay/40) + 5 + DefRegSet}
/2} + 2
= Int { { Int( 8.5 ) + 5 + 7 } /2 } + 2
= Int { 10 } + 2
= 12 byte times
Note: Please note that you might have to do this process
several times before you can get the actual defer register
setting for a desired defer time based on your delays.
Algorithm for Defer Time Calculations for 10 Mbit
Serial Mode
Defer Time = Int {{Int(Delay/100)+17+DefRegSet}/8}+2
Defer Time = The transmit defer time in byte times
Delay = Delay from the down going edge of TXEN to the
down going edge of CSN. (Half Duplex)
= 0 (Full Duplex)
DefRegSet = The transmit defer register setting
Int = Using the Whole Number Portion
Example Calculations
To find out the value that needs to be programmed
into the defer register for a defer time of 9600 ns, the
following steps need to be taken
Assume Delay = 3400 ns
Desired Defer Time = 9600 ns = 12 byte times
The desired byte times should be a multiple of 800
Step 1: Calculation of the Actual Defer Time
Let’s assume a Defer Register Setting Value of 21
Defer Time = Int { { Int (Delay / 100) + 17 + DefRegSet}
/8} + 2
= Int { { Int (34) + 17 + 21}/8} + 2
= Int {9} + 2
= 9 + 2 = 11 byte times
Step 2: Calculation of the Actual Defer Register
Setting
Since we know that the value derived from the
previous step is 1 byte time lower than what is
desired we will increment the assumed defer
register setting by 8 and do the calculations again.
Let’s assume a Defer Register Setting Value of 29
Defer Time = Int {{Int (Delay / 100)+17+DefRegSet}
/8} + 2
= Int { { Int (34) + 17 + 29 } /8} + 2
= Int { 10 } + 2
= 10 + 2 = 12 byte times
Please note that you might have to do this process
several times before you can get the actual defer
register setting for a desired defer time based on your
delays.
3.6.10 Transmit Control/Product I.D. Register
The ower four bits can be used to set a threshold value on
the transmit FIFO that can be used to control the packet
transmission and the upper four bits of this register con-
tains the product I.D. When the lower four bits are written
with a decimal value ranging rom 1 o 15, packet ransmis-
sion from the FIFO will begin only when the count of the
double words of data written nto the transmit FIFO equals
or exceeds twice the register value. For example, when
the lower four bits are written with a decimal value of 15,
data transmission will begin only after the FIFO is written
with 30 or more double words of data. This hreshold value
is valid only at the beginning of frame transmission and it
will take effect again when the user starts to load the
beginning of the next frame. The default decimal value of
the lower four bits is ‘0’ and packet transmission will begin
automatically when the FIFO is loaded with a minimum of
one double word of data. The upper four bits are read only
and contain a value of ‘C’.
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