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參數(shù)資料
| 型號： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 10/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-10
MD400158/D
Pin
147
Pin Name
RX_DV_2
I/O
I
Description
Receive Data Valid Port 2
In MII mode this input is receive data valid. Receive data valid becomes active with
the first nibble of synchronized and decoded Preamble or SFD appearing on the
RXD[3:0]_2 lines and goes inactive one clock time after the last nibble of the frame
is received. This is an active high input.
171
CSN_3
I
Carrier Sense Port 3
This is port #3's carrier sense input which indicates there is traffic on the transmission
medium connected to port #3. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
170
RX_DV_3
I
Receive Data Valid Port 3
In MII mode this input is receive data valid. Receive data valid becomes active with
the first nibble of synchronized and decoded Preamble or SFD appearing on the
RXD[3:0]_3 lines and goes inactive one clock time after the last nibble of the frame
is received. This is an active high input.
191
CSN_4
I
Carrier Sense Port 4
This is port #4's carrier sense input which indicates there is traffic on the transmission
medium connected to port #4. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
190
RX_DV_4
I
Receive Data Valid Port 4
In MII mode this input is receive data valid. Receive data valid becomes active with
the first nibble of synchronized and decoded Preamble or SFD appearing on the
RXD[3:0]_4 lines and goes inactive one clock time after the last nibble of the frame
is received. This is an active high input.
145
COLL_1
I
Collision Port 1
This input indicates that a transmission contention has occurred on the transmission
medium connected to port #1. The collision input is latched internally. Sampled
during transmission, Collision is set by an active high pulse on the COLL input and
automatically reset at the end of transmission of the JAM sequence.
168
COLL_2
I
Collision Port 2
This input indicates that a transmission contention has occurred on the
transmission medium connected to port #2. The collision input is latched
internally. Sampled during transmission, Collision is set by an active
high pulse on the COLL input and automatically reset at the end of
transmission of the JAM sequence.
187
COLL_3
I
Collision Port 3
This input indicates that a transmission contention has occurred on the
transmission medium connected to port #3. The collision input is latched
internally. Sampled during transmission, Collision is set by an active high
pulse on the COLL input and automatically reset at the end of transmission
of the JAM sequence.
204
COLL_4
I
Collision Port 4
This input indicates that a transmission contention has occurred on the
transmission medium connected to port #4. The collision input is
latched internally. Sampled during transmission, Collision is set by an
active high pulse on the COLL input and automatically reset at the end
of transmission of the JAM sequence.
Pin Description (cont.)
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