參數(shù)資料
型號(hào)： 84301
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 5/62頁(yè)
文件大?。?/td> 606K
代理商： 84301
84301 4-Port
Fast Ethernet Controller
4-5
MD400158/D
Pin
44, 57
64, 73
Pin Name
TXRDY_[1:4]
I/O
O
Description
Transmit Ready
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s transmit FIFO has enough space
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s transmit FIFO has greater than or equal to the threshold number of double word
spaces available in the FIFO and a low value indicates it does not. The tristate drivers
for all these outputs are enabled by a low value on the TXINTEN input pin.
42, 56
63, 72
RXRDY_[1:4]
O
Receive Ready
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s receive FIFO has enough data
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s receive FIFO has greater than or equal to the threshold number of double
words available in the FIFO or has a completed receive packet in the FIFO as
indicated by the packets status double word being in the FIFO. The tristate drivers
for all these outputs are enabled by a low value on the RXINTEN input pin.
39
SPDTAVL
O
Space Data Available
This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO during
a write operation. For further details, please refer to the Transmit Data Write Timing
and the Receive Data Read Timing diagrams.
40
RXTXEOF
I/O
Receive Transmit End of Frame
This is a bidirectional pin that is used to signal the last double word of a transmit or
receive packet. During receive FIFO reads this pin is enabled as an output and when
detected high indicates that the last double word of a receive packet has been read
from the receive FIFO. During transmit FIFO writes this pin is an input and when
asserted high during a write it indicates that this is the final double word of a transmit
packet. In the transmit FIFO write case the value of this signal is stored as the 33rd
bit in the FIFO. In the receive FIFO read case the value of this signal is read out as
the 33rd bit of the receive FIFO.
41
TXNOCRC
I
Transmit No CRC
This active high input is used to control appending of a CRC to a transmit packet.
A transmit packet can be made to exclude appending a CRC value if this input is held
high any time during a packet write to the transmit FIFO. Transmission of all packets
without CRC can be done by setting bit #4 of configuration register #1. It should be
noted that TXNOCRC pin can be used to control CRC encapsulation only on a per
packet basis.
Receive/Transmit Data
This is the bidirectional data bus for reads from the receive FIFO or writes to the
transmit FIFO of the chip. Bus direction is controlled via RXINTEN and RXDEN for
reads; TXINTEN and TXWREN are used for writes. Data is clocked with the
RXRD_TXWR strobe input.
80-84
86-89
91-94
96-101
107-112
115-121
RXTXDATA[31:0]
I/O
Pin Description (cont.)
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