參數(shù)資料
型號: 84301
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(4端口快速以太網(wǎng)控制器)
文件頁數(shù): 34/62頁
文件大小: 606K
代理商: 84301
84301 4-Port
Fast Ethernet Controller
4-34
MD400158/D
Configuration Register #3
Mode A:
Bit 0 - When written to a 1 this bit programs the 84301
into bidirectional byte enable mode. In this mode the
RXTXBE 3:0] pins act as nputs during Transmit FIFO
write operations and as outputs during Receive FIFO
read operations. When this bit is 0 the RXTXBE [3:0]
pins are input only. The value of this bit after reset is
0.
Mode B: Status Non-Appendage Mode
Bit 1 - When written to a 1 this bit stops the 84301 from
including a status double word n the Receive FIFO at
the end of receive packet data. When this bit is 0 any
packet received without discard will include a status
double word in the FIFO. The value of this bit after
reset is 0.
Note:
If both this bit and bit 2 of configuration
register #2 have been written to a 1, the chip will
behave as if bit 2 of configuration register #2 were
a 0. In other words only one EOF, occurring on the
last double word of data, will be read out and no
status double word will occur during reading of the
receive packet data.
Mode C: 32 Bit-Mode for Some Counters
Bit 2 - When written to a 1 this bit enables the full 32-
bit size of the following counters.
CRC Error Counters
Short Frame Counter
Oversize Frame Counter
Dribble Error Counter
Receive Collision Counter
When this bit is 0 the above counters behave as 16-
bit counters. The value of this bit after reset is 0.
Note:
This bit must be written to 1 before interrupts
for these counters can be enabled using bits 6
through 2 of the Counter Interrupt Mask Register
#2. Otherwise, these counters will never cause an
interrupt condition or set any of the interrupt status
bits in the Interrupt Status Register #2.
Mode D: Counter Operations
Bit 3 - This bit controls the effect that completion of a
read operation to a management counter has upon
that counters next value in the following ways:
Counter Reset Mode
When written to a 1 - Upon reading the least
significant byte of a management counter, the
counter value will either be reset to 00000000 hex
or preloaded to a value other than 00000000 hex if
there was an attempt to update the counter during
the time the counter value was frozen due to a read
operation in progress. (Please see counter de-
scription section).
Counter Incrementing Mode
When written to a 0 - Upon reading the least
significant byte of a management counter, the
counter will either maintain its present value, or be
incremented if there was an attempt to update the
counter during the time the counter value was
frozen due to a read operation in progress.
Bit
0
Value
‘1’
Definition
Sets the Chip into Bidirectional
Byte Enable Mode.
When this bit is set, the status
double word will be prevented
from being appended to the end of
a packet received.
Enables 32 bit mode for some
counters.
Counter Reset Mode
Counter Incrementing Mode
Unused
Unused
Unused
Unused
R/W
R/W
Default
0
Mode
A
1
‘1’
R/W
0
B
2
‘1’
R/W
0
C
3
‘1’
‘0’
R/W
0
D
4
5
6
7
R
R
R
R
0
0
0
0
7
6
5
4
3
2
1
0
Configuration Register #3
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