參數(shù)資料
型號(hào): 84301
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(4端口快速以太網(wǎng)控制器)
文件頁數(shù): 7/62頁
文件大小: 606K
代理商: 84301
84301 4-Port
Fast Ethernet Controller
4-7
MD400158/D
Pin
Pin Name
I/O
Description
Media Independent Interface
138
TXC_1
I
Transmit Clock Port 1
This is the transmit clock input for port #1. In standard 10 Mbit/sec Serial Mode, this
is a 10 Mhz, 50% duty cycle transmit clock used to synchronize the transmit data from
port #1 to the encoder. In this mode, transmit data appears serially on the TXD0_1
output and all transitions of transmit data and the TXEN_1 output occur from the
falling edge of the clock. In MII mode, this is a 2.5/25 Mhz, 50% duty cycle clock, and
the transmit data appears on the TXD0_1 through TXD3_1 outputs. In this mode
transitions of transmit data and the TXEN_1 output occur from the rising edge of the
clock.
161
TXC_2
I
Transmit Clock Port 2
This is the transmit clock input for port #2. In standard 10 Mbit/sec Serial Mode, this
is a 10 Mhz, 50% duty cycle transmit clock used to synchronize the transmit data from
port #2 to the encoder. In this mode, transmit data appears serially on the TXD0_2
output and all transitions of transmit data and the TXEN_2 output occur from the
falling edge of the clock. In MII mode, this is a 2.5/25 Mhz, 50% duty cycle clock, and
the transmit data appears on the TXD0_2 through TXD3_2 outputs. In this mode
transitions of transmit data and the TXEN_2 output occur from the rising edge of the
clock.
177
TXC_3
I
Transmit Clock Port 3
This is the transmit clock input for port #3. In standard 10 Mbit/sec Serial Mode, this
is a 10 Mhz, 50% duty cycle transmit clock used to synchronize the transmit data from
port #3 to the encoder. In this mode, transmit data appears serially on the TXD0_3
output and all transitions of transmit data and the TXEN_3 output occur from the
falling edge of the clock. In MII mode, this is a 2.5/25 Mhz, 50% duty cycle clock, and
the transmit data appears on the TXD0_3 through TXD3_3 outputs. In this mode
transitions of transmit data and the TXEN_3 output occur from the rising edge of the
clock.
197
TXC_4
I
Transmit Clock Port 4
This is the transmit clock input for port #4. In standard 10 Mbit/sec Serial Mode, this
is a 10 Mhz, 50% duty cycle transmit clock used to synchronize the transmit data from
port #1 to the encoder. In this mode, transmit data appears serially on the TXD0_4
output and all transitions of transmit data and the TXEN_4 output occur from the
falling edge of the clock. In MII mode, this is a 2.5/25 Mhz, 50% duty cycle clock, and
the transmit data appears on the TXD0_4 through TXD3_4 outputs. In this mode
transitions of transmit data and the TXEN_4 output occur from the rising edge of the
clock.
139-142
TXD[3:0]_1
O
Transmit Data Port 1
In standard 10 Mbit/sec Serial Mode, TXD0_1 is the serial transmit data output from
port #1 to the encoder. In MII mode, these outputs drive a nibble of transmit data
every leading edge of the TXC_1 clock from port #1 to the encoder.
162, 163
164, 166
TXD[3:0]_2
O
Transmit Data Port 2
In standard 10 Mbit/sec Serial Mode, TXD0_2 is the serial transmit data output from
port #2 to the encoder. In MII mode, these outputs drive a nibble of transmit data
every leading edge of the TXC_2 clock from port #2 to the encoder.
180, 181
182, 185
TXD[3:0]_3
O
Transmit Data Port 3
In standard 10 Mbit/sec Serial Mode, TXD0_3 is the serial transmit data output from
port #3 to the encoder. In MII mode, these outputs drive a nibble of transmit data
every leading edge of the TXC_3 clock from port #3 to the encoder.
Pin Description (cont.)
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