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參數(shù)資料
| 型號(hào)： | 84301 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 33/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-33
MD400158/D
to the multicast address filter register depending on
bits 0 to 5 of the CRC. If the corresponding bit is a ‘1’
it will receive the frame, otherwise it will discard the
frame.
Mode E: Receive Without Discard Mode
When his bit s written “High”, packets will be received
without discarding even if the RXABORT goes high
during reception.
Mode F1/F2: Pack Only Two Valid Bytes in First
Receive Double Word/SQE Status, Bit 5
Mode F1: When this bit is written HIGH, the first
double word of data written to the receive FIFO for a
receive packet will have only two valid bytes. When
this first double word is read out of the receive FIFO,
which wo bytes are valid depends on whether he port
has been programmed for Big Endian or Little Endian
data formats. Thus, if bit 7 of Configuration Register
#2 (Endianess selection) is set HIGH (Big Endian),
RXTXDATA[15:0] will be valid or he irst double word
read; if bit 7 is set LOW (Little Endian),
RXTXDATA[31:16] will be valid. All subsequent
double words of data read from the receive FIFO will
contain 4 valid bytes except for the last double word
which may not have all 4 bytes valid.
Note
: This mode s available only f the chip s used n
non-bidirectional byte enable operating mode.
Mode F2: Reading this bit provides SQE test result.
The SQE function is always on; reading this register
causes an automatic reset of this bit value to “zero”.
Mode G: Successful Packet Transmission Com-
plete Feature
This feature is programmable by setting bit 7 of
configuration register #2 to a 1’ value. If this bit s set,
then, independent of the FIFO threshold setting, the
corresponding port’s TXRDY pin will go LOW once
the final double word of data for a transmit packet is
written to the transmit FIFO. Once a port’s TXRDY
has been driven LOW due to this condition, it will
remain LOW until he packet has completed ransmis-
sion without error or until a transmission exception
condition causing the TXRET pin to go HIGH is
cleared. This allows the user to determine when a
packet has completed successful transmission by
detecting when the corresponding port’s TXRDY
goes HIGH after the final double word of the packet
has been written. After TXRDY goes LOW due to a
double word write with the RXTXEOF pin HIGH,
further writes to the transmit FIFO are allowed as ong
as the SPDTAVL pin indicates that there is still space
available within the transmit FIFO.
Mode H: Big Endian Mode
Writing this bit HIGH programs the port to Big Endian
mode.
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