參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 56/57頁(yè)
文件大?。?/td> 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
56
Address
15
13
Data
0
Ah
Sig
ID
Reserved
Bh
SubSystem ID
Ch
Sub System Vendor ID
EEPROM field description:
Bits 15-14:
Sig
The Sig field is a signature of 01 which indicates to the 82557C that there is a valid
EEPROM present. If the Sig field is not 01 the other bits are ignored and the default
values are used.
Bit 13:
ID
The ID bit indicates how to use the SubSystem ID and SubSystem Vendor ID fields as
described in section 8.2.
SubSystem Vendor and Device ID will be read directly into PCI Configuration space as described in section 8.2.
EEPROM READ instruction waveform is shown below:
A
0
A
1
EECS
EESK
EEDI
EEDO
A
5
A
4
A
2
D
1
D
0
READ OP code
A
3
A
0
Figure 24. EEPROM Read Instruction Waveform
The automatic read of the EEPROM can be disabled by setting the TCK pin (pin #140) to 0 during the
deassertion of RST#. If the 82557C notices that TCK is 0, it does not attempt to read the EEPROM and the ID
fields maintain their default values.
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