參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 47/57頁(yè)
文件大小： 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
47
6.4.2.2.
MII and 10 Mbps Interface Timings
Table 20 provides the timing parameters for MII and serial interface signals.
Table 20. MII and Serial Interface Timing Parameters
Symbol
Parameter
Min
Max
Units
Notes
T24
tvalTX
tsuRX
thRX
thiloMDC
TX Synchronous Signals Valid Time
0
15
ns
1, 3
T25
RX Synchronous Signals Setup Time
10
ns
2, 3
T26
RX Synchronous Signals Hold Time
10
ns
2, 3
T27
MDC high/low Time
200
ns
5, 7
310
ns
5, 8
T28
tvalMD
MDC to MDIO Valid Delay
50
440
ns
6, 7
50
580
ns
6, 8
T29
TsuMDIO
MDIO Setup Time
120
ns
6, 7
120
ns
6, 8
T30
thMDIO
MDIO Hold Time
0
ns
6
NOTES:
1.
2.
3.
4.
TX Synchronous Signals are: TXD0-3 and TXEN (RTS in serial interface).
RX Synchronous Signals are: RXD0-3, RXDV and RXER.
The timing reference is the rising edge of TXCLK, for transmit, or RXCLK, for receive.
To drive an MII cable (Z
= 68
± 15%, Length @ 0.5m) a 40
± 10% resistor should be connected in series with
each MII output (TXD0-3, TXEN, MDC and MDIO).
MDC is an aperiodic signal.
Referenced to rising edge of MDC.
These timings apply when the PCI clock rate is 33 MHz. As the PCI clock rate references the MDC/MDIO interface,
these timngs scale accordingly.
These timings apply when the PCI clock rate is 25 MHz. As the PCI clock rate references the MDC/MDIO interface,
these timngs scale accordingly.
The MDC/MDIO timings are specified as measured at the 82557, and as required or supplied by the 82557.
10. CRS and COL (CLD in serial interface) are asynchronous with regard to either RXCLK or TXCLK.
5.
6.
7.
8.
9.
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