參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 34/57頁(yè)
文件大?。?/td> 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
34
is asserted at this same time. The CRS signal is
expected to be asserted before one slot time has
elapsed, however the transmission will complete
successfully even if CRS is not asserted (the
absence of CRS will be reported in a status bit). In
the case of a collision, the PHY asserts the COL
signal on the 82557 which will then stop transmitting
the frame within four clock times and append a JAM
sequence onto the link.
After the end of a collided transmission, the 82557
will back off and attempt to retransmit once the
backoff timer expires. Note that the retransmission is
done from the data stored internally in the 82557
FIFO block, so no re-access to the data in host
memory is performed. In the case of a successful
transmission, the 82557 is ready to transmit any
other frames queued in its FIFO block within the
minimum inter frame spacing (IFS) of the link.
4.3.1.2.
10/100 Mbps MII Reception
Frame reception starts with the assertion of CRS
(while the 82557 is not transmitting) by the PHY.
Once RXDV is asserted, 82557 will begin sampling
incoming data on pins RXD0-3 on the rising edge of
RXC. There is a minimum of four RXC clock periods
from assertion of CRS until the 82557 samples the
first RCV data nibble from the PHY. The 82557
accepts frames which pass its address filtering
mechanism, passing the frame in a byte-wide format
to its internal FIFO block. Reception ends when CRS
is deasserted by the PHY. The last nibble sampled
by the 82557 is the nibble present on RXD0-3 on the
RXCLK rising edge in which RXDV deassertion is
detected and CRS is still asserted.
During reception the RXDV (Receive Data Valid)
signal is asserted to the 82557. If the 82557 detects
the assertion of RXER while RXDV is asserted, it will
designate this frame as a corrupted frame by setting
an error bit in the status field of the frame. The 82557
will continue to receive the incoming frame
regardless of the RXER signal. RXDV should remain
deasserted while no reception is taking place.
4.3.2.
10/100 MII MBPS FULL DUPLEX
OPERATION
When operating in full duplex mode the 82557 can
transmit and receive frames simultaneously. In full
duplex mode the CRS signal is associated with
received frames only and has no affect on
transmitted frames. Similarly, COL is associated with
transmission only and does not affect received
frames.
Transmission starts when TXEN goes active.
Transmission starts regardless of the state of CRS.
Reception starts when the CRS signal is asserted
indicating traffic on the RCV pair of the PHY.
4.3.3.
10 MBPS-ONLY INTERFACE
The 10 Mbps mode is fully compliant with the IEEE
802.3 CSMA/CD standard. It interfaces to 10 Mbps-
only PHY devices such as the Intel 82503. The 10
Mbps serial interface is bit wide. Transmission is
performed on the TXD0 pin and reception on RXD0.
Serial data is clocked on the rising edge of the clock;
TXCLK for transmission and RXCLK for reception.
These clocks operate at 10 MHz and are both driven
by the PHY.
4.3.3.1.
10 Mbps Transmission
When the 82557 has a frame ready for transmission,
it samples the link for activity. If the CRS signal is
inactive (no activity on the link), frame transmission
begins. The data is transmitted via TXD0 and is
clocked on the rising edge of TXC. The RTS signal is
asserted at this time. The CRS signal is expected to
be asserted before one slot time has elapsed,
however the transmission will complete successfully
even if CRS is not asserted (the absence of CRS will
be reported in a Lost CSR status bit). In the case of
a collision, the PHY asserts the COL signal to the
82557 which will then stop transmitting the frame
within four clock times and append a JAM sequence
onto the link. After the end of a collided transmission
the 82557 will back off and attempt to transmit once
again when the back off timer expires. Note that the
retransmission is done from the data stored internally
in the 82557 FIFO block, so no re-access to the data
in host memory is performed. In the case of a
successful transmission, the 82557 is ready to
transmit any other frames queued in its FIFO block
within the minimum IFS of the link.
4.3.3.2.
10 Mbps Reception
Frame reception starts with the assertion of CRS by
the PHY. The 82557 will then start sampling
incoming data on RXD0 on the rising edge of RXC.
There is a PHY-dependant delay of two or more
clock cycles between the assertion of CRS and the
first data bit the 82557 samples. The 82557 accepts
frames which pass its address filtering mechanism
and passes the frame in a byte-wide format to its
internal FIFO block. Reception ends when CRS is
deasserted by the PHY. The last bit sampled by the
相關(guān)PDF資料
PDF描述
82559 Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
8255A-5 PROGRAMMABLE PERIPHEAL INTERFACE
8255A IC LOGIC 3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER -40+85C SSOP-16 - OBSOLETE
8255A Programmable Peripheral Interface iAPX86 Family
8255A-5 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC; Package: SOIC - Wide; No of Pins: 24; Temperature Range: Industrial
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
8255702-025 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk
8255702-095 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk
8255702-096 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk
8255702-098 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk
8255704-050 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*