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參數(shù)資料
| 型號： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 33/57頁 |
| 文件大?。?/td> | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
33
4.2.2.
SERIAL EEPROM INTERFACE
The Serial EEPROM, a Hyundai HY93C46 or
equivalent IC, stores configuration data for the
82557. The EEPROM is a serial in/serial out device.
Serial EEPROMs range in size from 16 to 256
registers of 16 bits per register. All accesses, either
read or write, are preceded by a command instruction
to the device. The command instructions, begin with
a logical 1 as a start bit, two op code bits (indicating
RD, WR, Erase, etc.) and n-bits of address. The
address field varies with the size of the EEPROM,
for example 6 bits for a 64 register EEPROM, or 8
bits for a 256 register device, etc. The end of the
address field is indicated by a dummy 0 bit from the
EEPROM which indicates the entire address field
has been transferred to the device. A command is
issued by asserting the CS signal and clocking the
data into the EEPROM on its Data In input relative to
the SK (Shift Clock) input. The Chip Select signal is
deasserted after completion of the EEPROM cycle
(Command, Address and Data). Figure 15 shows the
EEPROM timing diagram.
The
82557 User’s Manual
describes EEPROM
access port and instruction sets.
434616
Figure 15. 82557 EPROM Timing Diagram (Example Read from Address 0)
4.3.
10/100 Mbps CSMA/CD Unit
The 82557 CSMA/CD unit implements both the
IEEE802.3 10 Mbps and IEEE802.3u Fast Ethernet
100 Mbps standards. It performs all the CSMA/CD
protocol functions such as transmission, reception,
collision handling, etc. The 82557 CSMA/CD unit
operates in two modes of operation; a 10/100 Mbps
MII compatible mode, in which the data stream is
nibble-wide and the serial clocks run at either 25 or
2.5 MHz, or a 10 Mbps-only mode, in which the data
stream is bit-wide and the clocking is at 10 MHz.
Selection of either MII compatible mode or 10 Mbps-
only mode is by configuration.
The MII compatible mode, along with an MII-
compatible
10/100
Serial
automatically between either 10 or 100 Mbps
operation depending on the speed of the network to
which it is attached. During frame transmission, byte
wide data is accepted from the 82557 internal FIFO
block. The CSMA/CD unit builds the IEEE 802.3
frame format and depending on the mode, the frame
is either transmitted as a bit stream (10 Mbps-only
mode) or as a nibble stream (10/100 Mbps MII
mode). During frame reception the CSMA/CD unit
converts the bit stream (10 Mbps-only mode) or
PHY,
switches
nibble stream (10/100 Mbps MII mode) to a byte wide
format, strips off the frame delimiters, such as the
preamble and SFD and then passes the data to the
82557 internal FIFO block from where it is deposited
into host system memory via the 82557 PCI Bus
Master interface.
4.3.1.
10/100 MBPS MII COMPATIBLE
INTERFACE
The CSMA/CD unit provides the functional interface
to any MII compatible serial PHY. The data path
consists of a separate nibble-wide stream for both
transmit and receive activities. Data transfers are
clocked by the 25 MHz transmit and receive clocks
in 100 Mbps operation, or by 2.5 MHz clocks in 10
Mbps operation. These clock inputs are driven by the
PHY.
4.3.1.1.
10/100 Mbps MII Transmission
When the 82557 has a frame ready for transmission,
it samples the link for activity. If the CRS signal is
inactive (no activity on the link), frame transmission
begins. The data is transmitted via pins TXD0-3,
clocked on the rising edge of TXC. The signal TXEN
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