參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 19/57頁(yè)
文件大?。?/td> 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
19
Table 3. PCI Command Register Bits
Bit #
Bit Name
Description
0
IO Space
This bit controls a device's response to I/O space accesses. A value of 0
disables the device response. A value of 1 allows the device to respond
to I/O space accesses. The specific implementation of this bit in the
82557 is configurable with default value 0 .
1
Mem Space
This bit controls a device's response to memory space accesses. A
value of 0 disables the device response. A value of 1 allows the device to
respond to memory space accesses. This bit is configurable in the 82557
with a default value 0.
2
Bus Master
This bit controls a device's ability to act as a master on the PCI bus. A
value of 0 disables the device from generating PCI accesses. A value of
1 allows the device to behave as a bus master. This bit is configurable in
the 82557 with a default value 0.
3
Special Cycle
This bit controls a device's action on Special Cycle operations. A value of
0 causes the device to ignore all Special Cycle operations. This bit is
always set to 0 in the 82557.
4
Mem WR & Invalidate En
This is an enable bit for using the Memory Write and Invalidate command.
This bit is always set to 0 in the 82557 (disabled).
5
VGA Palette Snoop
This bit controls how VGA compatible devices handle accesses to their
palette registers. This bit is always set to a 0 in the 82557 (disabled).
6
Parity Error Response
This bit controls the 82557’s response to parity errors. When the bit is
set, the 82557 takes its normal action when a parity error is detected.
When the bit is reset, the 82557 ignores any parity errors that it detects
and continues normal operation. This bit must be set to 0 after RST#.
This bit is configurable in the 82557 with a default value 0.
7
Wait Cycle Control
This bit, when set to a 1, is used to control whether or not a device does
address/data stepping. This bit is always set to 0 in the 82557 (disabled).
8
Serr Enable
This bit is an enable bit for the SERR# driver. A value of 0 disables the
SERR# driver. A value of 1 enables the SERR# driver. This bit (and bit 6,
PERR# Enable) must be on to report address parity errors. This bit is
configurable in the 82557 with a default value of 0.
9
Fast Back to Back Enable
This bit controls whether or not a master can do fast back-to-back
transactions to different devices. This bit is set to a 0 in the 82557, fast
back-to-back transactions are only allowed to the same agent.
10-15
Reserved
Reserved. These bits are hardwired to 0 in the 82557.
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