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參數(shù)資料
| 型號： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 15/57頁 |
| 文件大?。?/td> | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
15
Receive and Command units of the Micro Machine
allows the 82557 to execute commands and receive
incoming frames simultaneously, with no real-time
CPU intervention.
The 82557 contains an interface to both an external
FLASH memory and an external serial EEPROM.
The FLASH interface, which could also be used to
connect to any standard 8-bit EPROM device,
provides up to 1 Mbyte of addressing to the FLASH.
It utilizes a multiplexed address scheme that works
in conjunction with an LS373 or compatible latch to
de-multiplex the address. Without the latch, up to 16
Kbytes can be addressed. Both Read and Write
accesses are supported. The FLASH may be used
for remote boot functions, network statistical and
diagnostics functions, etc. The FLASH is mapped
into host system memory (anywhere within the 32-bit
memory address space) for software accesses. It is
also mapped into an available boot expansion ROM
location during boot time of the system. For more
information on the FLASH interface, see Section
4.1.3. The EEPROM is used to store relevant
information for a LAN connection such as Node
Individual Address, as well as board manufacturing
and configuration information. Both Read and Write
accesses to the EEPROM are supported by the
82557. For more information on the EEPROM
interface, see Section 4.1.3.
3.2.
FIFO Subsystem Overview
The 82557 FIFO subsystem consists of a 3 Kbyte
transmit FIFO and 3 Kbyte receive FIFO. Each FIFO
is unidirectional and independent of the other. The
FIFO subsystem serves as the interface between the
82557 parallel side and the serial CSMA/CD unit. It
provides a temporary buffer storage area for frames
as they are either being received or transmitted by
the 82557. This allows for several important features
in the 82557:
Transmit frames can be queued within the XMT
FIFO, allowing back to back transmission within
the minimum Inter Frame Spacing (IFS)
The storage area in the FIFO area allows the
82557 to withstand long PCI Bus latencies
without losing incoming data or corrupting
outgoing data.
The 82557 XMT FIFO Threshold allows the
transmit start threshold to be tuned to eliminate
underruns while concurrent transmits are being
performed.
The FIFO subsection allows extended PCI 0
Wait State burst accesses to or from the 82557
for both RCV and XMT frames, since the transfer
is to the FIFO storage area as opposed to
directly to the serial link.
Transmissions
resulting
Underrun) are retransmitted directly from the
82557
FIFO,
increasing
eliminating the need to reaccess this data from
the host system.
Incoming Runt RCV Frames (less than the legal
minimum
frame
size)
automatically by the 82557 without transferring
this faulty data to the host system.
in
errors
(CDT,
performance
and
can
be
discarded
3.3.
10/100 Mbps Serial CSMA/CD
Unit Overview
The CSMA/CD unit of the 82557 allows it to be
connected to either a 10 or 100 Mbps Ethernet
network. The 82557 interfaces to either an IEEE
802.3 10/100 Mbps MII compatible PHY device or a
10 Mbps-only IEEE 802.3 PHY. In the case of the
MII compatible PHY, the 82557 can switch
automatically between 10 or 100 Mbps operation
depending on the speed of the network. The
CSMA/CD unit performs all of the functions of the
802.3 protocol such as frame formatting, frame
stripping, collision handling, deferral to link traffic,
etc. The CSMA/CD unit can also be placed in a Full
Duplex mode which allows for simultaneous
transmission and reception of frames. The CSMA/CD
unit accepts data from the 82557 XMT FIFO and
converts it to either serial or nibble-wide (MII
Compatible mode) data for transmission on the link.
During reception, the CSMA/CD unit converts data
from either serial or nibble-wide data to a byte-wide
format and transfers it to the RCV FIFO of the
82557. The CSMA/CD unit contains a Management
Data Interface (MDI) to an MII compliant PHY. This
allows control and status parameters to be passed
between the 82557 and the PHY (parameters
specified by software) by one serial pin and a
clocking pin, reducing the number of control pins
needed for PHY mode control.
相關(guān)PDF資料 |
PDF描述 |
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| 82559 | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 8255A-5 | PROGRAMMABLE PERIPHEAL INTERFACE |
| 8255A | IC LOGIC 3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER -40+85C SSOP-16 - OBSOLETE |
| 8255A | Programmable Peripheral Interface iAPX86 Family |
| 8255A-5 | 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC; Package: SOIC - Wide; No of Pins: 24; Temperature Range: Industrial |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8255702-025 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
| 8255702-095 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
| 8255702-096 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
| 8255702-098 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
| 8255704-050 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
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