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參數(shù)資料
| 型號： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 25/57頁 |
| 文件大小： | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
25
PCI Configuration Cycles
As already mentioned, the PCI definition provides for
totally software driven initialization and configuration
via a separate configuration address space. This
section provides a description of the PCI commands
for accessing the PCI configuration space. For more
concise information please refer to the latest revision
of the
PCI Local Bus Specification.
For normal accesses (i.e., memory or I/O), each
device decodes its own addresses. In configuration
accesses, the device selection decoding is done
externally, and signaled to the PCI device via the
IDSEL pin. The 82557 becomes the target of a
configuration command (RD or WR) only if its IDSEL
is asserted and AD0-1 are 00 during the address
phase of the command. The addressed register in
the configuration space is determined by AD2-7 and
BE0-3# lines. The 82557 will support non-burst
configuration accesses of a BYTE, WORD, or
DWORD. Read and Write configuration cycles are
shown in Figure 7 and Figure 8 respectively.
434608
Figure 7. Configuration Read Cycle
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PDF描述 |
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| 82559 | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 8255A-5 | PROGRAMMABLE PERIPHEAL INTERFACE |
| 8255A | IC LOGIC 3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER -40+85C SSOP-16 - OBSOLETE |
| 8255A | Programmable Peripheral Interface iAPX86 Family |
| 8255A-5 | 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC; Package: SOIC - Wide; No of Pins: 24; Temperature Range: Industrial |
相關(guān)代理商/技術(shù)參數(shù) |
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