參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 23/57頁(yè)
文件大?。?/td> 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
23
0
Base Address
1
2
3
4
Prefetchable
Set to one if there are no side effects on reads, the device returns all
bytes on reads regardless of the byte enables, and host bridges can
merge processor writes into this range without causing errors.
Memory space indicator
00 - locate anywhere in 32 bit address space
01 - locate below 1 Meg
10 - locate anywhere in 64 bit address space
11 - reserved
0
Type
434605
Figure 4. Base Address Register for Memory Mapping
0
31
Base Address
1
0
IO space indicator
Reserved
1
2
434606
Figure 5. Base Address Register for I/O
Bit 0 in all base registers is read-only and used to
determine whether the register maps into Memory or
I/O space. Base registers that map to Memory space
must return a 0 in bit 0. Base registers that map to
I/O space must return a 1 in bit 0.
Base registers that map into I/O space are always 32
bits with bit 0 hardwired to a 1, bit 1 is reserved and
must return 0 on reads, and the other bits are used to
map the device into I/O space.
The number of upper bits that a device actually
implements depends on how much of the address
space the device will respond to. For example, a
device that wants a 1 Mbyte memory address space
would set the most significant 12 bits of the base
address register to be configurable, setting the other
bits to 0.
For its Control/Status Registers (CSR), the 82557
requires one Base Address Register to I/O Map
these registers, and one Base Address Register to
Memory Map these registers anywhere within the 32-
bit memory address space. It is up to the software
driver to determine which Base Address Register (I/O
or
Memory)
to
use
Control/Status registers. Both are always requested
by the 82557. The 82557 requires one Base Address
Register to map the accesses to an optional FLASH
memory. The size of the space requested is 1
Mbyte, and it is always mapped anywhere in the 32-
bit memory address space. Table 6 describes the
implementation of the Base Address Registers in the
82557.
to
access
the
82557
相關(guān)PDF資料
PDF描述
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