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參數(shù)資料
| 型號： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
30
434613
Figure 12. Flash Buffer Write Cycle
System Error:
The 82557 reports parity error on
address phase using the SERR# pin. If the SERR#
Enable bit (in the PCI-configuration command
register) or the Parity Error Response bit are not set,
the 82557 only sets the Detected Parity Error bit
(PCI Status Register, bit 15). If SERR# Enable and
Parity Error Response bits are both set, the 82557
sets the Signaled System Error bit (PCI Status
Register, bit 14) as well as the Detected Parity Error
bit and asserts SERR# for one clock.
The 82557, when detecting system error, will claim
the cycle if it was the target of the transaction and
continue the transaction as though the address was
correct.
NOTE
The 82557 will report a system error for any
parity error on address phase, whether or not
it is involved in the current transaction.
82557 Bus Master Operation
As a PCI Bus Master, the 82557 initiates memory
cycles to fetch data for transmission or deposit
received data and for accessing the memory resident
control structures. The 82557 performs zero wait
state burst read and write cycles to the host main
memory. Figure 13 and Figure 14 depict memory
read and write burst cycles. For bus master cycles,
the 82557 is the initiator and the host main memory
(or the PCI Host Bridge depending on the
configuration of the systems) is the target.
The CPU provides the 82557 with action commands
and pointers to the data buffers that reside in host
main memory. The 82557 independently manages
these structures and initiates burst memory cycles to
transfer data to and from them. The 82557 uses
MEM-RD Multiple for burst accesses to data buffers
and MEM-RD LINE for burst accesses to control
structures (commands, pointers, etc.). For all write
burst accesses to either data or control, the 82557
uses the MEM-WR command only.
Read Accesses:
The 82557 performs block transfers
from host system memory in order to perform frame
transmission on the serial link. In this case, the
82557 initiates zero wait state memory read burst
cycles for these accesses. The length of a burst is
bounded by the system and also by the 82557
internal FIFO. The length of a read burst may also be
bounded by the TX DMA MAXIMUM BYTE COUNT
in the Configuration command.
The 82557, as the initiator, drives the address lines
AD0-31, the command and byte enable lines C/BE0-
3# and the control lines IRDY# and FRAME#. The
82557 asserts IRDY# to support zero wait state burst
相關(guān)PDF資料 |
PDF描述 |
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| 82559 | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 8255A-5 | PROGRAMMABLE PERIPHEAL INTERFACE |
| 8255A | IC LOGIC 3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER -40+85C SSOP-16 - OBSOLETE |
| 8255A | Programmable Peripheral Interface iAPX86 Family |
| 8255A-5 | 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC; Package: SOIC - Wide; No of Pins: 24; Temperature Range: Industrial |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 8255702-096 | 制造商:ITT Interconnect Solutions 功能描述:NASA CONNECTOR - Bulk |
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