參數(shù)資料
型號(hào)： 82557
廠商： Intel Corp.
英文描述： Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
中文描述： 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器）
文件頁(yè)數(shù)： 36/57頁(yè)
文件大小： 601K
代理商： 82557
INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
36
PREAMBLE
At the beginning of each transaction, the 82557 sends a sequence of 32 contiguous logic
one bits on the MDIO pin with corresponding cycles on the MDC clock pin for
synchronization by the PHY.
ST
A Start of Frame pattern of 01.
OP
An Operation Code which can assume one of two values:
10
Read
01
Write
PHYAD
A 5 bit address of the PHY device which provides support for 32 unique PHY addresses.
The 82557 will drive the value written into the PHYAD portion of the MDI register in this
field.
REGAD
A 5 bit address of the specific register within the PHY device. This provides support for 32
unique registers. The desired register address is specified by the value written to the MDI
register.
TA
A two-bit turnaround time during which no device actively drives the MDIO signal on a read
cycle. During a read transaction the PHY should not drive MDIO in the first bit time and
drive a 0 in the second bit time. During a write transaction the 82557 will drive a ‘10’ pattern
to fill this time.
DATA
16 bits of data driven by the PHY on read transactions or by the 82557 on write
transactions. This data is either control or status parameters passed between the 82557 and
the PHY.
IDLE
The IDLE condition on MDIO is a high impedance state. The MDIO driver is disabled, and
the PHY should pull-up the MDIO line to a logic one.
5.0.
82557 SOFTWARE INTERFACE
5.1.
The Shared Memory
Communication Architecture
The
communication system with the host CPU. This
shared memory is divided into three parts: the
Control/Status Registers (CSR), the Command Block
List (CBL), and the Receive Frame Area (RFA). The
CSR resides on-chip and can be accessed by either
I/O or memory cycles, while the rest of the 82557
memory structures reside in system (host) memory.
82557
establishes
a
shared
memory
The first 8 bytes of the CSR is called the System
Control Block (SCB). The SCB serves as a central
communication point for exchanging control and
status information between the host CPU and the
82557.
The host software controls the state of the 82557
Command Unit (CU) and Receive Unit (RU) (i.e.,
Active, Suspended or Idle) by writing commands to
the SCB. The 82557 posts the status of the CU and
RU in the SCB Status word and indicates status
changes with an interrupt. The SCB also holds
pointers to a linked list of action commands called
the CBL and a linked list of receive resources called
the RFA. Figure 16 shows this type of structure.
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