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參數(shù)資料
| 型號(hào)： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 46/57頁 |
| 文件大小： | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
46
Table 18. Serial Interface Clock Specifications
Symbol
Parameter
Min
Typical
Max
Units
Notes
T8
tcycTXC
t
TXC Cycle Time
99.99
100.01
ns
T9
TXC Duty Cycle
35
50
65
%
T10
t
TXC rise/fall Time
5
ns
T11
tcycRXC
t
RXC Cycle Time
100
ns
T12
RXC Duty Cycle
35
65
%
T13
t
RXC rise/fall Time
5
ns
NOTES:
1.
No specific phase relationship is assumed between TXC and RXC.
6.4.2.
TIMING PARAMETERS
6.4.2.1.
PCI Timings
Table 19 provides the timing parameters for the 82557 PCI interface.
Table 19. PCI Timing Parameters
Symbol
Parameter
Min
Max
Units
Notes
T14
tval
tval(ptp)
ton
toff
tsu
tsu(ptp)
th
trst-clk
trst-off
CLK to Signal Valid Delay: bused signals
2
11
ns
1, 2, 3
T15
CLK to Signal Valid Delay: point to point
2
12
ns
1, 2, 3
T16
Float to Active Delay
2
ns
1
T17
Active to Float Delay
28
ns
1
T18
Input Set up Time to CLK: bused signals
7
ns
3, 4
T19
Input Set up Time to CLK: point to point
10
ns
3, 4
T20
Input Hold Time from CLK
0
ns
4
T22
Reset Active Time After CLK Stable
100
μ
s
5
T23
Reset Active to Output Float delay
40
ns
5, 6
NOTES:
1.
2.
See timing measurement conditions diagram in this section.
Minimum times are specified with 0 pF equivalent load; maximum times are specified with 50 pF equivalent load.
Actual test capacitance may vary, but results are correlated to these specifications.
REQ# and GNT# are point-to-point signals, and have different output valid delay and input setup times than do
bused signals. All other signals are bused.
See timing measurement conditions in this section.
RST# is asserted and deasserted asynchronously with respect to CLK.
All PCI bus output drivers are floated when RST# is active.
3.
4.
5.
6.
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