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參數(shù)資料
| 型號(hào)： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
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Table 6. 82557 Base Address Registers
Register Location
Description
10h
Memory space for the 82557 Control/Status Registers. The size of this space is 4
Kbytes. It will be marked as a prefetchable space and is mapped anywhere in the
32-bit memory address space.
14h
I/O space for 82557 Control/Status Registers. The size of this space is 32 bytes.
18h
Memory space for the 82557 flash buffer for accesses above 1 Mbyte. The size of
this space is 1 Mbyte. It will be marked as a non-prefetchable space and is mapped
anywhere in the 32-bit address space.
1C-27h
Reserved. 82557 returns 0.
0
31
Expansion ROM Base Address
(Upper 21 bits)
Address decode enable
Reserved
1
10
11
434607
Figure 6. Expansion ROM Base Address Register Layout
Table 7. 82557 Expansion ROM Base Address Register Format
31
20 19
1
0
Read/Write
Reserved (all 0’s)
En
Expansion ROM Base Address Register
The 82557 provides an interface to a local FLASH (or
EPROM) which can be used as an expansion ROM.
A 32-bit Expansion ROM Base Address Register at
offset 30h in the configuration space is defined to
handle the address and size information for boot-time
access to the FLASH. Figure 6 shows how this
register is organized. The register functions exactly
like a 32-bit Base Address register except that the
encoding (and usage) of the bottom bits is different.
(The upper 21 bits correspond to the upper 21 bits of
the Expansion ROM base address.) The 82557
allows its Expansion ROM to be mapped on any
1Mbyte boundary. The most significant 12 bits are
configurable to indicate the 1Mbyte size requirement.
Bit 0 in the register is used to control whether or not
the device accepts accesses to its expansion ROM.
When this bit is reset, the devices Expansion ROM
address space is disabled. This bit is programmed at
initialization time by the system BIOS. The Memory
Space bit in the Command register has precedence
over the Expansion ROM enable bit. A device
responds to accesses to its expansion ROM only if
both the Memory Space bit and the Expansion ROM
Base Address Enable bit are set to 1 (it is reset to 0
on Reset).
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PDF描述 |
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| 82559 | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
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