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參數(shù)資料
| 型號： | 82557 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器) |
| 中文描述： | 快速以太網(wǎng)PCI總線控制器（快速以太網(wǎng)的PCI總線控制器） |
| 文件頁數(shù)： | 45/57頁 |
| 文件大?。?/td> | 601K |
| 代理商： | 82557 |
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INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER
45
6.4.
Timing Specification
6.4.1.
CLOCK SPECIFICATIONS
6.4.1.1.
PCI Interface Clock
The 82557 uses the PCI clock. Figure 17 shows the
clock waveform and required measurement points for
the PCI clock signal. Table 16 summarizes the PCI
clock specifications. This clock waveform should be
treated as the minimum for the 82557.
6.4.1.2.
MII Interface Clock
The 82557 uses two clocks on the MII interface:
transmit clock (TXCLK) and receive clock (RXCLK).
Table 17 shows timings for each clock.
6.4.1.3.
10 Mbps Serial Interface Clock
The 82557 uses two clocks on the serial interface:
transmit clock TXC and receive clock RXC. Table 17
shows timings for both clocks.
Table 16. PCI Clock Specifications
Symbol
Parameter
Min
Max
Units
Notes
T1
tcyc
thigh
tlow
-
CLK Cycle Time
30
ns
1
T2
CLK High Time
11
ns
T3
CLK Low Time
11
ns
T4
CLK Slew Rate
1
4
V/ns
2
NOTES:
1.
2.
The 82557 will work with any PCI clock frequency up to 33 MHz.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate should be met across the
minimum peak-to-peak portion of the clock waveform as shown in Figure 17.
Table 17. MII Clock Specifications
Symbol
Parameter
Min
Typical
Max
Units
Notes
T5
tcyc100
TXC/RXC Cycle Time @ 100 Mbps
operation
40
ns
1, 2, 3
T6
tcyc10
TXC/RXC Cycle Time @ 10 Mbps
operation
400
ns
1, 2, 3
T7
DC
TXC/RXC Duty Cycle
35
65
%
1, 2, 3
NOTES:
1.
Either high or low times of RXCLK may be extended at the event of switching it from recovered clock to TXCLK, or
vice versa.
No specific phase relationship is assumed between TXCLK and RXCLK.
When RXDV is active, the frequency difference between TXCLK and RXCLK should not exceed ± 200 ppm.
2.
3.
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