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IDT EJTAG System
EJTAG Test Access Port
79RC32438 User Reference Manual
20 - 69
November 4, 2002
Notes
ProbTrap
14
Controls location of the debug exception
vector:
0:
Normal memory 0xBFC0 0480
1:
in dmseg at 0xFF20 0200
When this bit is changed, then it is guaran-
teed that the new value is indicated to the
processor when it can be read back here.
This handshake mechanism ensures that
the setting from the JTAG_TCK clock
domain takes effect in the processor clock
domain.
However, a change of the ProbTrap prior
to setting the EjtagBrk bit will be effective
at the debug exception.
Not all combinations of ProbEn and Prob-
Trap are allowed, see section“Combina-
tions of ProbTrap and ProbEn” on page 20-
70.
R/W
See section
“EJTAG-
BOOT Indica-
tion
Determines
Reset Value
of EjtagBrk,
ProbTrap and
ProbEn” on
page 20-70
Required
EjtagBrk
12
Requests a Debug Interrupt exception to
the processor when this bit is written as 1.
The debug exception request is ignored if
the processor is already in debug at the
time of the request. A write of 0 is ignored.
The debug request restarts the processor
clock if the processor was in a low-power
mode.
The read value indicates a pending Debug
Interrupt exception requested through this
bit:
0:
No pending Debug Interrupt exception
requested through this bit
1:
Pending Debug Interrupt exception
The read value can, but is not required to,
indicate other pending DINT debug
requests (for example, through the DINT
signal).
This bit is cleared by hardware when the
processor enters Debug Mode.
R/W1
See section
“EJTAG-
BOOT Indica-
tion
Determines
Reset Value
of EjtagBrk,
ProbTrap and
ProbEn” on
page 20-70
Required
DM
3
Indicates if the processor is in Debug
Mode:
0:
Processor is in Non-Debug Mode
1:
Processor is in Debug Mode
R
0
Required
0
28:23, 17,
13, 11:4,
2:0
Must be written as zeros; return zeros on
reads.
0
0
Required
Fields
Description
Read/
Write
Reset
State
Compli-
ance
Name
Bit
Table 20.48 EJTAG Control Register Field Description (Part 4 of 4)