IDT MIPS32 4Kc Processor Core
Exceptions
79RC32438 User Reference Manual
2 - 45
November 4, 2002
Notes
Entry Vector Used:
General exception vector (offset 0x180)
TLB Refill Exception — Instruction Fetch or Data Access
During an instruction fetch or data access, a TLB refill exception occurs when no TLB entry in a TLB-
based MMU matches a reference to a mapped address space and the EXL bit is 0 in the Status register.
Note that this is distinct from the case in which an entry matches but has the valid bit off. In that case, a TLB
Invalid exception occurs.
Cause Register ExcCode Value:
TLBL: Reference was a load or an instruction fetch
TLBS: Reference was a store
Additional State Saved:
Entry Vector Used:
TLB refill vector (offset 0x000) if StatusEXL = 0 at the time of exception;
general exception vector (offset 0x180) if StatusEXL = 1 at the time of exception.
TLB Invalid Exception — Instruction Fetch or Data Access (4Kc core)
During an instruction fetch or data access, a TLB invalid exception occurs in one of the following cases:
No TLB entry in a TLB-based MMU matches a reference to a mapped address space; and the EXL
bit is 1 in the Status register
A TLB entry in a TLB-based MMU matches a reference to a mapped address space, but the
matched entry has the valid bit off
The virtual address is greater than or equal to the bounds address in a FM-based MMU.
Cause Register ExcCode Value:
TLBL: Reference was a load or an instruction fetch
TLBS: Reference was a store
Additional State Saved:
EntryHi
VPN2
UNPREDICTABLE
EntryLo0
UNPREDICTABLE
EntryLo1
UNPREDICTABLE
Register State
Value
BadVAddr
Failing address
Context
The BadVPN2 fields contains VA
31:13
of the failing
address.
EntryHi
The VPN2 field contains VA
31:13
of the failing address; the
ASID field contains the ASID of the reference that missed.
EntryLo0
UNPREDICTABLE
EntryLo1
UNPREDICTABLE
Table 2.22 CP0 Register States on a TLB Refill Exception
Register State
Value
Table 2.21 CP0 Register States on an Address Exception Error (Part 2 of 2)