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IDT RC32438 Device Overview
Pin Description
79RC32438 User Reference Manual
1 - 18
November 4, 2002
Notes
MII0TXCLK
I
Ethernet 0 MII Transmit Clock.
This clock is a continuous clock that provides a
timing reference for the transfer of transmit data.
MII0TXD[3:0]
O
Ethernet 0 MII Transmit Data.
This nibble wide data bus contains the data to
be transmitted.
MII0TXENP
O
Ethernet 0 MII Transmit Enable.
The assertion of this signal indicates that data
is present on the MII for transmission.
MII0TXER
O
Ethernet 0 MII Transmit Coding Error.
When this signal is asserted together
with MIITXENP, the ethernet PHY will transmit symbols which are not valid data
or delimiters.
MII1CL
I
Ethernet 1 MII Collision Detected.
This signal is asserted by the ethernet PHY
when a collision is detected.
MII1CRS
I
Ethernet 1 MII Carrier Sense.
This signal is asserted by the ethernet PHY
when either the transmit or receive medium is not idle.
MII1RXCLK
I
Ethernet 1 MII Receive Clock.
This clock is a continuous clock that provides a
timing reference for the reception of data.
MII1RXD[3:0]
I
Ethernet 1 MII Receive Data.
This nibble wide data bus contains the data
received by the ethernet PHY.
MII1RXDV
I
Ethernet 1 MII Receive Data Valid.
The assertion of this signal indicates that
valid receive data is in the MII receive data bus.
MII1RXER
I
Ethernet 1 MII Receive Error.
The assertion of this signal indicates that an
error was detected somewhere in the ethernet frame currently being sent in the
MII receive data bus.
MII1TXCLK
I
Ethernet 1 MII Transmit Clock.
This clock is a continuous clock that provides a
timing reference for the transfer of transmit data.
MII1TXD[3:0]
O
Ethernet 1 MII Transmit Data.
This nibble wide data bus contains the data to
be transmitted.
MII1TXENP
O
Ethernet 1 MII Transmit Enable.
The assertion of this signal indicates that data
is present on the MII for transmission.
MII1TXER
O
Ethernet 1 MII Transmit Coding Error.
When this signal is asserted together
with MIITXENP, the ethernet PHY will transmit symbols which are not valid data
or delimiters.
MIIMDC
O
MII Management Data Clock.
This signal is used as a timing reference for
transmission of data on the management interface.
MIIMDIO
I/O
MII Management Data.
This bidirectional signal is used to transfer data
between the station management entity and the ethernet PHY.
EJTAG/ICE
EJTAG_TMS
I
EJTAG Mode
. The value on this signal controls test operation of the EJTAG
Controller.
JTAG_TCK
I
JTAG Clock
. This is an input test clock, used to clock the shifting of data into or
out of the boundary scan logic, JTAG Controller or the EJTAG Controller.
JTAG_TCK is independent of the system and the processor clock with nominal
50% duty cycle.
JTAG_TDI
I
JTAG Data Input
. JTAG mode: This is the serial data input to where data is
shifted into the boundary scan logic, JTAG Controller, or the EJTAG Controller.
Signal
Type
Name/Description
Table 1.1 Pin Description (Part 8 of 9)