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IDT Table of Contents
79RC32438 User Reference Manual
x
November 4, 2002
Notes
I2C Bus Master Status Mask Register...........................................................................15-11
I2C Bus Slave Interface...........................................................................................................15-12
Example of I2C Bus Transaction....................................................................................15-12
I2C Bus Slave Status Register.......................................................................................15-14
I2C Bus Slave Status Mask Register.............................................................................15-15
I2C Bus Slave Address Register....................................................................................15-17
I2C Bus Slave Acknowledge Register............................................................................15-18
Programming Example............................................................................................................15-18
16 Serial Peripheral Interface
Functional Overview..................................................................................................................16-1
Block Diagram ...........................................................................................................................16-1
SPI Clock Prescalar...................................................................................................................16-3
Clock Prescalar Register..................................................................................................16-3
SPI Control Register ........................................................................................................16-4
SPI Status Register..........................................................................................................16-5
SPI Data Register ............................................................................................................16-6
SPI Setup...................................................................................................................................16-7
Serial Bit I/O Pins.......................................................................................................................16-7
Serial I/O Function Register.............................................................................................16-7
Serial I/O Configuration Register .....................................................................................16-8
Serial I/O Data Register...................................................................................................16-9
Master Programming Example................................................................................................16-10
SPI Initialization..............................................................................................................16-10
17 On-Chip Memory
Introduction................................................................................................................................17-1
Theory of Operation...................................................................................................................17-1
On-chip Memory Base Register.......................................................................................17-1
On-chip Memory Mask Register.......................................................................................17-2
18 Debugging and Performance Monitoring
Introduction................................................................................................................................18-1
Features.....................................................................................................................................18-1
Debug and Performance Register Description..........................................................................18-1
IPBus Monitor............................................................................................................................18-2
IPBus Monitor Registers............................................................................................................18-3
IPBus Monitor Trigger Configuration Register..................................................................18-3
IPBus Monitor Trigger Select Register.............................................................................18-6
IPBus Monitor Manual Trigger Register...........................................................................18-8
IPBus Monitor Trigger Condition 0 Register.....................................................................18-9
IPBus Monitor Trigger Condition 1 Register.....................................................................18-9
IPBus Monitor Trigger Condition 2 Register...................................................................18-10
IPBus Monitor Trigger Condition 3 Register...................................................................18-10
IPBus Monitor Filter Select Register..............................................................................18-11
IPBus Monitor Filter Control 0 Register..........................................................................18-12
IPBus Monitor Filter Control 1 Register..........................................................................18-13
IPBus Monitor Filter Control 2 Register..........................................................................18-13