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參數(shù)資料
| 型號(hào)： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 79/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
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75
Table 23. Partition and Erase-Block Region Information
Bottom
Offset
(1)
P = 39H
Top
Offset
(1)
P = 39H
Description
(Optional Flash Features and Commands)
See Table 24
Length
Address
Bottom
Top
(P+18)h
(P+18)h
Number of device hardware-partition regions within the device
x = 0: a single hardware partition device (no fields follow)
x specifies the number of device partition regions containing one
or more contiguous erase block regions.
1
51:
51:
Partition Region 1 Information
Bottom
Offset
(1)
P = 39H
Top
Offset
(1)
P = 39H
Description
(Optional Flash Features and Commands)
See Table 24
Length
Address
Bottom
52:
53:
54:
Top
52:
53:
54:
(P+19)h
(P+1A)h
(P+1B)h
(P+19)h
(P+1A)h
(P+1B)h
Number of identical partitions within the partition region
2
Simultaneous program and erase operations allowed in other
partitions while this partition is in read mode
bits 0–3 = number of simultaneous program operations
bits 4–7 = number of simultaneous erase operations
Simultaneous program and erase operations allowed in other
partitions while this partition is in program mode
bits 0–3 = number of simultaneous program operations
bits 4–7 = number of simultaneous erase operations
Simultaneous program and erase operations allowed in other
partitions while this partition is in erase mode
bits 0–3 = number of simultaneous program operations
bits 4–7 = number of simultaneous erase operations
Partitions' erase block regions in this Partition Region.
1. x = 0 = no erase blocking; the Partition Region erases in “bulk”
2. x specifies the number of erase block regions containing
one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Partition Region 1 Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
1
(P+1C)h
(P+1C)h
1
55:
55:
(P+1D)h
(P+1D)h
1
56:
56:
(P+1E)h
(P+1E)h
1
57:
57:
(P+1F)h
(P+20)h
(P+21)h
(P+22)h
(P+23)h
(P+24)h
(P+25)h
(P+1F)h
(P+20)h
(P+21)h
(P+22)h
(P+23)h
(P+24)h
(P+25)h
4
58:
59:
5A:
5B:
5C:
5D:
5E:
58:
59:
5A:
5B:
5C:
5D:
5E:
Partition 1 (Erase Region 1)
Minimum block erase cycles x 1000
Partition 1 (erase region 1) bits per cell; internal error correction
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserved for future use
Partition 1 (Erase Region 1) page mode and synchronous mode
capabilities as defined in
Table 19
.
bit 0 = page mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
2
1
(P+26)h
(P+26)h
1
5F:
5F:
(P+27)h
(P+28)h
(P+29)h
4
60:
61:
62:
(P+2A)h
63:
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