參數(shù)資料
型號(hào)： 28F320D18
廠商： Intel Corp.
英文描述： 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器)
中文描述： 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 22/83頁(yè)
文件大小： 836K
代理商： 28F320D18
28F320D18
18
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4.6
Block Erase Command
The two-cycle Block Erase command initiates one block erase at the addressed block within the
selected partition. After writing the command, the device automatically outputs status register data
when any address within the partition is read. The CPU can detect block erase completion by
analyzing the partition’s status register bit SR.7. The partition will remain in status register read
mode until another command is written to its CUI. Only one partition can be in an erase mode at a
time; the other partition must be in one of the read modes.
4.7
Program Command
A two-cycle command sequence written to the target partition initiates a program operation. Only
one partition can be in program mode at a time; the other partition must be in one of the read
modes.
Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies
the address and data. The WSM then takes over, controlling the internal program algorithm. After
the program sequence is written, the device automatically outputs status register data when read
(see
Figure 8, “Automated Program Flowchart” on page 26
). The CPU can detect the completion of
the program event by analyzing status register bit SR.7. When the program operation completes,
check status register bit SR.4 for an error flag (“1”). If an error is detected, check status register bits
SR.4, SR.3, and SR.1 to understand what caused the problem.
The status register of the partition being programmed can be examined by addressing any block
address. After examining the status register, it should be cleared if an error was detected before
issuing a new command. The partition remains in status register read mode until another command
is written to the CUI.
4.8
Block Erase Suspend/Resume Command
The Block Erase Suspend command allows block erase interruption to read or program data in
another block within the target partition. Once the block erase process starts, writing the Block
Erase Suspend command requests that the WSM suspend the block erase operation after a certain
latency period. The device continues to output status register data when read after the Block Erase
Suspend command is issued. Status Register bits SR.7 and SR.6 indicate when the block erase
operation has been suspended (both will be set to “1”). Specification t
WHRH2
defines the block
erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A Program command sequence can also be issued during erase suspend to program
data in other blocks. Using the Program Suspend command (see
Section 4.9
), a program operation
can be suspended during an erase suspend. The only other valid commands while block erase is
suspended are Read Status Register, Block Erase Resume, Lock Block, Unlock Block, Lock Down
Block and Set Read Configuration Register.
During a block erase suspend, the chip can go into a pseudo-standby mode by taking CE# to V
IH
,
which reduces active current draw. V
PP
must remain at V
PP1/2
while block erase is suspended.
WP# must also remain at V
IL
or V
IH
.
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