- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F320D18 (Intel Corp.) 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 54/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
28F320D18
50
Product Preview
this is the worst case delay. The delay will only take place once during a continuous burst access,
and if the burst sequence never crosses a 16-word boundary, the delay will never happen. When the
output delay is encountered, the WAIT# pin will be asserted. This signal should be fed into the
systems wait-state control logic or directly to the CPU.
The WAIT# output pin is gated by OE# and CE#. If either OE# or CE# go inactive, the WAIT#
output buffer turns off. An internal pull-up resistor holds WAIT# at a logic ’1’ state. The resistor
value is approximately 1 M
. This output configuration allows multiple banks of flash enable wire
ORing, as shown in
Figure 15, “WAIT# Pin Connection Using Multiple Flash Memory
Components” on page 45
. WAIT# can also be configured for a couple different characteristics to
help simplify system usage. It can be configured for assertion during the delay or one data cycle
before the delay.
7.3.7
Write Operations
Write operations are used to switch the memory device between modes, to initiate a program or
erase, to lock or unlock blocks, and to write memory to the device to be stored. Commands that
switch modes of the device or suspend/resume a program or erase take one write cycle. Commands
which initiate a program or erase or lock/unlock blocks take two write cycles. A program command
is required before each data word to be programmed into the flash device, even if multiple data
words are programmed back to back.
Write operations transpire as asynchronous operations, similar to other Intel Flash memory
families, such as Advanced or Advanced+ Boot Block and Fast Boot Block memory. The flash
memory latches the address during writes the same way as during reads. The data, as in all Intel
Flash memory components, is latched on the rising edge of CE# or WE#, whichever goes high first.
For a write cycle, WE# and CE# are interchangeable.
After completing a program or erase or program/erase suspend command, the flash device
automatically goes into read status mode. Any reads to the flash at this point will return status
register data. This data is not updated to the output pins continually, rather CE# and/or OE# need to
be toggled for updated status register data. After a Set Read Configuration Register command, the
flash device goes into read array mode.
7.4
Design Tools and Software
7.4.1
Design Tools
Several tools are available which will simplify designing in 1.8 Volt Dual-Plane Flash memory
components into a system. They include VHDL and Verilog bus functional models, Timing
Designer* files, and IBIS files. Some of these tools can be found on Intel’s website, otherwise they
can be obtained by contacting an Intel field representative. Visit http://developer.intel.com/design/
flash/swtools/ for more details.
7.4.2
Flash Data Integrator (FDI)
Intel
Flash Data Integrator software is a code plus data storage manager for use in real-time
embedded applications. This software enables code execution and data storage in a single flash
device. It handles parameter, data-stream, and packet storage, as well as sophisticated file-system
features like wear-leveling, power-loss recovery and block reclaims. By consolidating code and
data storage in a single flash device, FDI reduces component count, allowing decreases in board
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F320J5 | 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲(chǔ)器) |
| 28F640J5 | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) |
| 28F400B3 | SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 28F400BL-TB | 4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BV-TB | 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F320J3D75 | 制造商:undefined 功能描述: |
| 28F320J5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT |
| 28F320J5_02 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory |
| 28F320S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| 28F320S5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。