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Program Suspend Read Array state, row 56. Array data can now be read. When array data has been
read, the program can be resumed by writing the Program Resume command. The partition goes
back to program mode, then completes programming the device. The bottom partition is then idle,
and the top partition is still in erase suspend mode. The state table now shows the current state of
the top partition in row 77. An Erase Resume command resumes the erase. When the erase has
completed, both partitions are idle, and can accept new commands.
7.2.3
Addresses during Writes to Flash
In previous Intel Flash products such as the Fast Boot Block and Intel
StrataFlash memory
families, the address while writing a command was a don’t care. In 1.8 Volt Dual-Plane Flash
memory this address should be the address location to which the command is referring (see
Table 5
on page 15
). For example, the first address in a block erase command should be an address within
that block; the first address in a program command should be the address of the word to be
programmed.
7.3
System Design Considerations
7.3.1
CPU Compatibility
1.8 Volt Dual-Plane Flash memory supports two high-performance read modes:
Asynchronous page mode
Synchronous burst mode
These two read modes allow the processor, if capable, to achieve much higher bandwidth than was
previously possible using single read accesses. The asynchronous page mode is ideal for non-
clocked memory systems and is compatible with standard page-mode ROM. If the memory
subsystem has access to an external processor referenced clock, the synchronous burst mode can be
used for increased read performance, provided the clock frequency is below 40 MHz.
If the system CPU or ASIC does not support burst or page-mode reads, single synchronous and
asynchronous reads are possible.
Whether the flash component is in synchronous or asynchronous mode depends on the setting in
the Configuration Register. Setting bit 15 to 0 enables synchronous burst reads, and setting the bit
to 1 enables asynchronous reads.
Upon reset, the device defaults to asynchronous page mode, and is put into read array mode. This
corresponds to the state of most processors upon startup. It is important to reset the flash memory
device when the processor is reset. This is because when the processor returns from reset it will
request memory from the flash array. If the flash has not been reset, it is possible for it to be in read
status or read ID mode, which would then return unwanted data to the processor.
7.3.2
Flash Integrated Features
The key to enabling compatibility between 1.8 Volt Dual-Plane Flash memory and today’s burst-
capable microprocessors are 1.8 Volt Dual-Plane Flash memory’s integrated features. These
features, listed and explained below, help simplify and eliminate excess system interface logic.
Address Latch