參數(shù)資料
型號(hào)： 28F320D18
廠商： Intel Corp.
英文描述： 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器)
中文描述： 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 66/83頁(yè)
文件大?。?/td> 836K
代理商： 28F320D18
28F320D18
62
Product Preview
8.7
AC Write Characteristics
NOTES:
1. Read timing characteristics during block erase and program operations are the same as during read-only
operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to
Table 5 on page 15
for valid A
and D
for block erase or program.
5. V
should be held at V
until block erase or program success is determined.
6. Write pulse width (t
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
high (whichever goes high first). Hence, t
= t
= t
= t
= t
.
7. Write pulse width high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or
WE# going low (whichever goes low last). Hence, t
= t
= t
= t
WHEL
= t
EHWL
.
8. t
WHQV
after Read Query, Device Identifier or Protection Register command
=
AVQV
+
#
Sym
Parameter
(1,2)
Notes
Min
Max
Unit
W1
t
PHWL
(t
PHEL
)
RST# High Recovery to WE# (CE#) Going Low
3
150
ns
W2
t
ELWL
(t
WLEL
)
CE# (WE#) Setup to WE# (CE#) Going Low
6
0
ns
W3
t
WLWH
Write Pulse Width
6
70
ns
W4
t
VLVH
ADV# Pulse Width
10
ns
W5
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE#) Going High
4
70
ns
W6
t
AVWH
(t
AVEH
)
Address Setup to WE# (CE#) Going High
4
70
ns
W7
t
VLWH
(t
VLEH
)
ADV# Setup to WE# (CE#) Going High
83
ns
W8
t
AVVH
Address Setup to ADV# Going High
10
ns
W9
t
WHEH
(t
EHWH
)
CE# (WE#) Hold from WE# (CE#) High
0
ns
W10
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE#) High
0
ns
W11
t
WHAX
(t
EHAX
)
Address Hold from WE# (CE#) High
0
ns
W12
t
VHAX
Address Hold from ADV# Going High
9
ns
W13
t
WHWL
(t
WHWL
)
Write Pulse Width High
7
30
ns
W14
t
BHWH
(t
BHEH
)
WP# Setup to WE# (CE#) Going High
3
200
ns
W15
t
VVWH
(t
QVEH
)
V
PP
Setup to WE# (CE#) Going High
3
200
ns
W16
t
WHGL
(t
EHGL
)
Write Recovery before Read
0
ns
W17
t
QVBL
WP# Hold from Valid SRD
3, 5
0
ns
W18
t
QVVL
V
PP
Hold from Valid SRD
3, 5
0
ns
W19
t
WHQV
WE# high to data valid
3, 8
t
+ 50
ns
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