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參數(shù)資料
| 型號(hào)： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 37/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
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33
For example, if RCR.3 = 0 (wrap mode) and RCR.2-0 = 001 (4-word burst length), then possible
linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, and 3-0-1-2.
If RCR.3 = 1 (no-wrap mode) and RCR.2-0 = 001 (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR.3 = 1 not only enables limited non-
aligned sequential burst, but also reduces power by minimizing the number of internal read
operations.
The above 4-word burst sequences can also be achieved by setting RCR.2-0 bits for continuous
linear burst mode (111). However, significantly more power may be consumed. The 1-2-3-4
sequence, for example, will consume power during the initial access, again during the internal
pipeline lookup as the processor reads word 2, and possibly again, depending on system timing,
near the end of the sequence as the device pipelines the next 4-word sequence. RCR.3 = 1 (no-wrap
mode) mode reduces this excess power consumption.
7.1.1.3
Automatic Power Savings
Automatic Power Savings (APS) provides low-power operation during active mode, allowing the
flash to put itself into a low current state when not being accessed. After data is read from the
memory array, the device’s power consumption enters the APS mode where typical I
CC
current is
comparable to I
CCS
. The flash memory stays in this static state with outputs valid until a new
location is read.
7.1.1.4
Standby Power
With CE# at a logic-high level (V
IH
) and both partitions are in read mode, the flash memory is in
standby mode. Outputs (DQ
0
–DQ
15
) are placed in high-impedance state independent of the OE#
signal’s state. If CE# transitions to a logic-high during erase or program operations, the device
continues the operation, consuming corresponding active power until the operation completes.
7.1.1.5
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required, since
the device does not care which power supply, V
PP
,
V
CC
, or V
CCQ
, powers up first.
7.1.1.5.1
RST# Connection
The use of RST# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RST# to
the system reset signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
CC
voltages are above V
LKO
and V
PP
is active. Since both WE# and CE# must be low for a command write, driving either signal to V
IH
will
inhibit writes to the device. The CUI architecture provides additional protection since
alteration of memory contents can only occur after successful completion of the two-step command
sequences. The device is also disabled until RST# is brought to V
IH
, regardless of the state of its
control inputs. By holding the device in reset during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another level of memory protection.
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