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參數(shù)資料
| 型號： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲器） |
| 文件頁數(shù)： | 48/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
44
Product Preview
Read Configuration Register
Status Register
WAIT# Output
7.3.2.1
Address Latch
The address latch latches the address during read and write cycles. The internal address latch is
controlled by ADV#. When ADV# is low, the latch is open. The latch closes when ADV# is driven
high or upon the first rising (or falling) edge of CLK when ADV# is low. This stores the current
address on the bus into the flash memory device and lets the address bus change without affecting
the flash. This pin works the same in write operations; the address to be written to gets latched on
the rising ADV# edge. Since writes are asynchronous, CLK is ignored and the address is not
latched on the clock edge. During asynchronous reads the address latch does not need to be used,
but addresses must then stay stable during the entire read operation. If ADV# is not used, addresses
are latched on the rising edge of CE# during reads, and on the rising edge of CE# or WE# during
writes, whichever goes high first.
7.3.2.2
Read Configuration Register
The read configuration register is a 16-bit register which sets the device’s read configuration, burst
order, frequency configuration and burst length. This register is stored in volatile memory within
the memory device, and is initialized upon return from reset. With the Read Configuration
Register, features of the flash memory device can be easily changed. Previous flash memory
devices such as Advanced Boot Block and Intel StrataFlash memory families did not contain this
register; rather features in these devices were set in hardware and were unchangeable. Being able to
change these features allows a single flash memory component to have several different hardware
features, configurable by the user. This allows this flash chip to work with a wide array of
processors, regardless of their hardware requirements.
7.3.2.3
Status Register
1.8 Volt Dual-Plane Flash memory contains two status registers, one for each partition. Each one is
an eight-bit register which contains the current information about the write state machine, the logic
which controls programming and erasing the device’s memory blocks. This register will report if a
program or erase command had completed successfully, and if not, a reason for the error. Also this
register will report when a program or erase has been suspended, so that the processor can then
issue a program, erase, or read command. This register cannot be written to, only cleared, by
issuing the Clear Status Register command, or by resetting the device.
7.3.2.4
WAIT# Output
1.8 Volt Dual-Plane Flash memory supports four-word, eight-word, and continuous burst lengths.
In continuous burst length, or in 4- or 8-word burst accesses with RCR.3 = 1, an output ball,
WAIT# is provided to simplify CPU to memory communication. The WAIT# informs the system
when data is valid. At a logic 1, there is valid data on the bus, at a logic 0, the data on the bus is
invalid.
Figure 15, “WAIT# Pin Connection Using Multiple Flash Memory Components” on
page 45
, shows how the WAIT# signal can be OR’d for interface to a CPU, to use multiple flash
components.
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