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參數(shù)資料
| 型號： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲器） |
| 文件頁數(shù)： | 12/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
8
Product Preview
3.0
Principles of Operation
The 1.8 Volt Dual-Plane Flash memory component includes an on-chip Write State Machine
(WSM) to manage block erase and program. It allows for CMOS-level control inputs, fixed power
supplies, and minimal processor overhead with RAM-like interface timings.
3.1
Bus Operations
The local CPU reads and writes flash memory in-system. All flash memory read and write cycles
conform to standard microprocessor bus cycles.
3.1.1
Read
The flash memory’s bottom partition, whether top- or bottom-parameter configuration, has three
read modes available: read array, identifier/CFI codes, and status register. The top partition has
only read array and status register read modes. Each partition can be in one of its read modes
independent of the other partition’s mode. However simultaneous read commands in both
partitions are not allowed.
Page mode and synchronous burst mode for both partitions are enabled by writing the Set Read
Configuration Register command to any device address. This sets the read configuration, burst
order, burst length, and frequency configuration.
For all read operations, CE# must be driven active to enable the device. The device internally
decodes upper address inputs to determine which partition is activated.
OE# controls data outputs (DQ
0
–DQ
15
) onto the I/O bus when active. WE# must be at V
IH
.
3.1.2
Output Disable
With OE# at a logic-high level (V
IH
), the device outputs are disabled. Output pins DQ
0
–DQ
15
are
placed in a high-impedance state.
3.1.3
Standby
Deselecting the device by bringing CE# to a logic-high level (V
IH
) places the device in standby
mode, which substantially reduces device power consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If deselected during program or erase operation, the
device continues to consume active power until the program or erase operation is complete.
3.1.4
Write
The Command User Interface (CUI) does not occupy an addressable memory location within its
partition, but it must be accessed by the system processor at the correct partition address range.
Programming/erasing may occur in only one partition at a time. The other partition must be in one
of the read modes (see
Table 2 on page 9
).
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