參數(shù)資料
型號(hào)： 28F320D18
廠商： Intel Corp.
英文描述： 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器)
中文描述： 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲(chǔ)器）
文件頁數(shù)： 78/83頁
文件大?。?/td> 836K
代理商： 28F320D18
28F320D18
74
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Table 21. Protection Register Information
Offset
(1)
P = 39H
Length
Description
(Optional Flash Features and Commands)
Address
Hex Code
Value
(P+E)h
1
Number of Protection register fields in JEDEC ID space
“00h,” indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) protection register bytes. Some are
pre-programmed with device-unique serial numbers. Others are
user programmable. Bits 0–15 point to the protection register
lock byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC-plane physical high address
bits 16–23 = “n” such that 2
n
= factory pre-programmed bytes
bits 24–31 = “n” such that 2
n
= user programmable bytes
47:
--01
01
(P+F)h
(P+10)h
4
48:
49:
--80
--00
80h
00h
(P+11)h
4A:
--03
8 byte
(P+12)h
4B:
--03
8 byte
Table 22. Burst Read Information
Offset
(1)
P = 39H
Length
Description
(Optional Flash Features and Commands)
Address
Hex Code
Value
(P+13)h
1
Page-mode read capability
bits 0–7 = “n” such that 2
n
HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no read
page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
bits 3–7 =
Reserved
bits 0–2 “n” such that 2
n+1
HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h indicates
that the device is capable of continuous linear bursts that will
output data until the internal burst counter reaches the end of the
device’s burstable address space. This field’s 3-bit value can be
written directly to the read configuration register bits 0–2 if the
device is configured for its maximum word width. See offset 28h
for word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
4C:
--03
8 byte
(P+14)h
1
4D:
--03
3
(P+15)h
1
4E:
--01
4
(P+16)h
(P+17)h
1
1
4F:
50:
--02
--07
8
Cont
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