參數(shù)資料
型號： 28F128J3A
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器)
中文描述： 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器）
文件頁數(shù)： 9/58頁
文件大?。?/td> 574K
代理商： 28F128J3A
28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
3
Table 1. Lead Descriptions
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A
0
input buffer is turned
off when BYTE# is high).
A
1–
A
23
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle.
32-Mbit: A
0–
A
21
64-Mbit: A
0–
A
22
128-Mbit: A
0–
A
23
DQ
0–
DQ
7
INPUT/
OUTPUT
LOW-BYTE DATA BUS:
Inputs data during buffer writes and programming, and inputs commands
during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ
6–
DQ
are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register bit 7) to
determine WSM status.
DQ
8–
DQ
15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS:
Inputs data during x16 buffer writes and programming operations. Outputs
array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated
when the chip is de-selected, the outputs are disabled, or the WSM is busy.
CE
0
,
CE
1
,
CE
2
INPUT
CHIP ENABLES:
Activates the device’s control logic, input buffers, decoders, and sense amplifiers.
When the device is de-selected (see Table 2,
Chip Enable Truth Table
), power reduces to standby
levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE
0
, CE
, or CE
that enables the device. Device deselection occurs with the first edge of CE
0
,
CE
1
, or CE
2
that disables the device (see Table 2,
Chip Enable Truth Table
).
RP#
INPUT
RESET/ POWER-DOWN:
Resets internal automation and puts the device in power-down mode. RP#-
high enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OE#
INPUT
OUTPUT ENABLE:
Activates the device’s outputs through the data buffers during a read cycle. OE# is
active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command User Interface, the Write Buffer, and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse.
STS
OPEN
DRAIN
OUTPUT
STATUS:
Indicates the status of the internal state machine. When configured in level mode (default
mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate
program and/or erase completion. For alternate configurations of the STATUS pin, see the
Configurations command. Tie STS to V
CCQ
with a pull-up resistor.
BYTE#
INPUT
BYTE ENABLE:
BYTE# low places the device in x8 mode. All data is then input or output on DQ
0–
DQ
7
,
while DQ
DQ
float. Address A
selects between the high and low byte. BYTE# high places the
device in x16 mode, and turns off the A
0
input buffer. Address A
1
then becomes the lowest order
address.
V
PEN
INPUT
ERASE / PROGRAM / BLOCK LOCK ENABLE:
For erasing array blocks, programming data, or
configuring lock-bits.
With V
PEN
≤
V
PENLK
, memory contents cannot be altered.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
With V
CC
≤
V
LKO
, all write attempts to the flash memory are inhibited.
V
CCQ
OUTPUT
BUFFER
SUPPLY
OUTPUT BUFFER POWER SUPPLY:
This voltage controls the device’s output voltages. To obtain
output voltages compatible with system data bus voltages, connect V
CCQ
to the system supply voltage.
GND
SUPPLY
GROUND:
Do not float any ground pins.
NC
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
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