參數(shù)資料
型號(hào)： 28F128J3A
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲(chǔ)器)
中文描述： 3伏特英特爾StrataFlash存儲(chǔ)器（128兆位3伏地層的閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 52/58頁(yè)
文件大?。?/td> 574K
代理商： 28F128J3A
28F128J3A, 28F640J3A, 28F320J3A
46
PRODUCT PREVIEW
NOTES:
CE
X
low is defined as the first edge of CE
0
, CE
1
, or CE
2
that enables the device. CE
X
high is defined at the first edge of CE
0
, CE
1
,
or CE
that disables the device (see Table 2, Chip Enable Truth Table).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE# may be delayed up to t
-t
after the first edge of CE
0
, CE
1
, or CE
2
that enables the device (see
Table 2, Chip Enable Truth Table) without impact on t
ELQV
.
3. Sampled, not 100% tested.
4.
See Figures 14–16, Transient Input/Output Reference Waveform for V
= 5.0 V ±10%, Transient Input/
Output Reference Waveform for V
= 3.0 V –3.6 V or V
CCQ
= 2.7 V –3.6 V, and Transient Equivalent Testing
Load Circuit for testing characteristics.
5. For devices configured to standard word/byte read mode, R15 (t
) will equal R2 (t
).
6. When reading the flash array a faster t
GLQV
(R16) applies. Non-array reads refer to status register reads, query
reads, or device identifier reads.
0606_16
NOTE:
CE
low is defined as the first edge of CE
, CE
, or CE
that enables the device. CE
high is defined at
the first edge of CE
, CE
, or CE
that disables the device (see Table 2,
Chip Enable Truth Table
).
For standard word/byte read operations, R15 (t
) will equal R2 (t
).
When reading the flash array a faster t
GLQV
(R16) applies. Non-array reads refer to status register reads,
query reads, or device identifier reads.
Figure 18. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations
R1
R8
R10
High Z
R13
R11
R12
R6
R5
R4 or R16
R3
R7
R2
R9
Valid
Output
ADDRESSES [A
23
-A
3
]
V
IH
V
IL
V
IH
V
IL
Disabled (V
IH
)
CE
[E]
Enabled (V
IL
)
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
OE# [G]
WE# [W]
DATA [D/Q]
DQ
0
-DQ
15
V
CC
RP# [P]
BYTE# [F]
High Z
R14
ADDRESSES [A
2
-A
0
]
V
IH
V
IL
Valid
Output
R15
Valid
Output
Valid
Address
Valid
Address
Valid
Address
Valid
Output
Valid
Address
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