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參數(shù)資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數(shù)： | 27/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
21
4.6
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires an appropriate
address within the block to be erased (erase changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle
block erase sequence is written, the device automatically outputs status register data when read (see
Figure 10). The CPU can detect block erase completion by analyzing the output of the STS pin or
status register bit SR.7. Toggle OE#, CE
0
, CE
1
, or CE
2
to update the status register.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V
is
valid and V
= V
. If block erase is attempted while V
≤
V
, SR.3 and SR.5 will be set to
“1.” Successful block erase requires that the corresponding block lock-bit be cleared. If block erase
is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set to “1.”
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data when read after the Block Erase Suspend
command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase
operation has been suspended (both will be set to “1”). In default mode, STS will also transition to
V
OH
. Specification t
WHRH
defines the block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A program command sequence can also be issued during erase suspend to program
data in other blocks. During a program operation with block erase suspended, status register bit
SR.7 will return to “0” and STS output (in default mode) will transition to V
. However, SR.6 will
remain “1” to indicate block erase suspend status. Using the Program Suspend command, a
program operation can also be suspended. Resuming a suspended programming operation by
issuing the Program Resume command allows continuing of the suspended programming
operation. To resume the suspended erase, the user must wait for the programming operation to
complete before issuing the Block Erase Resume command.
The only other valid commands while block erase is suspended are Read Query, Read Status
Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V
.
After the Erase Resume command is written, the device automatically outputs status register data
when read (see Figure 11). V
must remain at V
(the same V
level used for block erase)
while block erase is suspended. Block erase cannot resume until program operations initiated
during block erase suspend have completed.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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