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參數資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數： | 45/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
39
5.4
Input Signal Transitions - Reducing Overshoots and
Undershoots When Using Buffers or Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory
devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory
specifications (see Section 6.1,
Absolute Maximum Ratings
). Many buffer/transceiver vendors now
carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.
Internal output-damping resistors diminish the nominal output drive currents, while still leaving
sufficient drive capability for most applications. These internal output-damping resistors help
reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-
drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When
considering a buffer/transceiver interface design to flash, devices with internal output-damping
resistors or reduced-drive outputs should be used to minimize
overshoots and undershoots. For
additional information, please refer to the AP-647
5 Volt Intel StrataFlash Memory Design
Guide
.
5.5
V
CC
, V
PEN
, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if V
or V
falls outside of
the specified operating ranges, or RP#
≠
V
. If RP# transitions to V
during block erase, program,
or lock-bit configuration, STS (in default mode) will remain low for a maximum time of t
+ t
until the reset operation is complete. Then, the operation will abort and the device will enter reset/
power-down mode. The aborted operation may leave data partially corrupted after programming,
or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit
configuration commands must be repeated after normal operation is restored. Device power-off or
RP# = V
IL
clears the status register.
The CUI latches commands issued by system software and is not altered by V
, CE
, CE
, or CE
2
transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/
power-down mode, or after V
CC
transitions below V
LKO
. V
CC
must be kept at or above V
PEN
during V
CC
transitions.
After block erase, program, or lock-bit configuration, even after V
transitions down to V
, the
CUI must be placed in read array mode via the Read Array command if subsequent access to the
memory array is desired. V
PEN
must be kept at or below V
CC
during V
PEN
transitions.
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lock-
bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for V
voltages above V
when V
is
active. Since WE# must be low and the device enabled (see Table 2,
Chip Enable Truth Table
) for a
command write, driving WE# to V
or disabling the device will inhibit writes. The CUI’s two-step
command sequence architecture provides added protection against data alteration.
Keeping V
below V
prevents inadvertent data alteration. In-system block lock and unlock
capability protects the device against inadvertent programming. The device is disabled while RP#
= V
IL
regardless of its control inputs.
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| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
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