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參數(shù)資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數(shù)： | 31/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
25
Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup
is first written. The device automatically outputs status register data when read (see Figure 13). The
CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or
status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can
only occur when V
and V
are valid. If a clear block lock-bits operation is attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5 will be set to “1.”
If a clear block lock-bits operation is aborted due to V
or V
transitioning out of valid range,
block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required
to initialize block lock-bit contents to known values.
4.15
Protection Register Program Command
The 3 Volt Intel StrataFlash memory includes a 128-bit protection register that can be used to
increase the security of a system design. For example, the number contained in the protection
register can be used to “mate” the flash component with other system components such as the CPU
or ASIC, preventing device substitution.
The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other
segment is left blank for customer designers to program as desired. Once the customer segment is
programmed, it can be locked to prevent reprogramming.
4.15.1
READING THE PROTECTION REGISTER
The protection register is read in the identification read mode. The device is switched to this mode
by writing the Read Identifier command (90H). Once in this mode, read cycles from addresses
shown in Table 20 or Table 21 retrieve the specified information. To return to read array mode,
write the Read Array command (FFH).
4.15.2
PROGRAMMING THE PROTECTION REGISTER
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for
byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the
device will latch in address and data and program the specified location. The allowable addresses
are shown in Table 20 or Table 21. See Figure 14 for the
Protection Register Programming
Flowchart
.
Any attempt to address Protection Program commands outside the defined protection register
address space will result in a status register error (program error bit SR.4 will be set to 1).
Attempting to program a locked protection register segment will result in a status register error
(program error bit SR.4 and lock error bit SR.1 will be set to 1).
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| 28F320J3A | 3 Volt Intel StrataFlash Memory(3 V 32M位英特爾StrataFlash存儲器) |
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| 28F128 | 3 Volt Intel StrataFlash Memory |
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| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
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