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參數(shù)資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數(shù)： | 26/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
20
PRODUCT PREVIEW
NOTES:
1. A
0
is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is
A
. Data is always presented on the low byte in x16 mode (upper byte contains 00h).
2.
X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory
map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration
is complete and whether the operation completed successfully. It may be read at any time by
writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until another valid command is written. Page-mode
reads are not supported in this read mode. The status register contents are latched on the falling
edge of OE# or the first edge of CE
0
, CE
, or CE
that enables the device (see Table 2,
Chip Enable
Truth Table
). OE# must toggle to V
or the device must be disabled (see Table 2,
Chip Enable
Truth Table
) before further reads to update the status register latch. The Read Status Register
command functions independently of the V
PEN
voltage.
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the Write State Machine completes or suspends the operation. Device I/O pins DQ
DQ
and
DQ
DQ
are placed in a high-impedance state. When the operation completes or suspends (check
status register bit 7), all contents of the status register are valid when read.
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits indicate various failure conditions (see Table 18).
By allowing system software to reset these bits, several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in sequence) may be performed. The status register
may be polled to determine if an error occurred during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions
independently of the applied V
voltage. The Clear Status Register command is only valid when
the WSM is off or the device is suspended.
Table 15. Identifier Codes
(1)
Code
Address(1)
Data
Manufacture Code
Device Code
00000
00001
00001
00001
X
0002
(2)
(00) 89
(00) 16
(00) 17
(00) 18
32-Mbit
64-Mbit
128-Mbit
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
DQ
0
= 0
DQ
0
= 1
DQ
1–7
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|---|---|
| 28F320J3A | 3 Volt Intel StrataFlash Memory(3 V 32M位英特爾StrataFlash存儲器) |
| 28F640J3A | 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器) |
| 28F128 | 3 Volt Intel StrataFlash Memory |
| 28F1602C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F3204C3 | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器) |
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|---|---|
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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